Pitch-Doubled Vertical Resistance Variable Memory Cell
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Solution Overview
Problem
Resistance variable memory devices such as PCRAM and RRAM face challenges in high volume manufacturability and reliability, with existing structures often requiring complex processes and resulting in high switching currents.
Innovation Solution
The development of a resistance variable memory cell structure with a vertically oriented pitch-doubled array, featuring a via with a diameter not greater than 20 nanometers, where a resistance variable material is exposed between two electrodes, and a spacer material is used to create two distinct memory cells within a single contact hole, reducing footprint and switching current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a conventional resistance variable memory cell structure is used, then the device can store data, but the switching current is high and the footprint is large
Solution Approach 1:
The patent transitions from a planar memory cell layout to a vertical three-dimensional structure. The memory cell extends vertically with the resistance variable material forming a columnar structure between upper and lower electrodes, enabling pitch doubling and reduced footprint while maintaining data storage functionality
Solution Approach 2:
The resistance variable material is segmented into distinct regions within the vertical structure, with different portions exposed at different heights between the upper and lower electrodes. This segmentation enables the formation of two independent memory cells within a single contact hole, effectively doubling the memory density
2Ease of manufacture
If existing memory cell structures are used, then data storage is achieved, but manufacturability is reduced due to complex processes
Solution Approach 1:
The patent merges the formation of two memory cells into a single contact hole structure, sharing common elements such as the lower electrode, resistance variable material column, and encapsulation layers. This integration simplifies the manufacturing process by reducing the number of separate fabrication steps required
Solution Approach 2:
The resistance variable material is deposited to a thickness that preliminarily ensures both upper and lower electrode surfaces will be exposed after etching. This preliminary sizing of the resistance variable material layer facilitates subsequent processing steps and ensures proper cell formation
3Reliability
If conventional memory structures are used, then reliability is maintained, but etch damage occurs during fabrication
Solution Approach 1:
The patent uses a controlled etch process that exploits the differential etch rates between the resistance variable material and surrounding dielectric materials. The etch selectively removes dielectric material to expose the resistance variable material surfaces while the material's inherent properties protect it from damage, converting a potentially harmful process into a beneficial selective exposure method
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances memory density and manufacturability by allowing pitch doubling and reduced switching current, while avoiding etch damage, offering a more reliable and efficient memory cell structure compared to previous methods.
Implementation Method 1
An RRAM device includes a variable resistive material, such as a transition metal oxide, that has varying resistance depending on voltages applied thereto. When a voltage equal to or greater than a set voltage is applied to the variable resistive material, the resistance of the variable resistive material decreases (e.g., ON state). When a voltage equal to or greater than a reset voltage is applied to the variable resistive material, the resistance of the variable resistive material increases (e.g., OFF state).
Implementation Method 2
The resistance state of the PCRAM cell may be altered by heating the cell with a programming current. This results in the PCRAM cell being programmed to a particular resistance state, which may correspond to a data state.
Implementation Method 3
The phase change material of a PCRAM device may exist in an amorphous, higher resistance state, or a crystalline, lower resistance state.
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 1E~1F
AI summary
Resistance variable memory cell structures and methods are described herein. One or more resistance variable memory cell structures include a first electrode common to a first and a second resistance variable memory cell, a first vertically oriented resistance variable material having an arcuate top surface in contact with a second electrode and a non-arcuate bottom surface in contact with the first electrode; and a second vertically oriented resistance variable material having an arcuate top surface in contact with a third electrode and a non-arcuate bottom surface in contact with the first electrode.