Vertical Resistive Element Reduces Chip Size and Bonding Wires
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Solution Overview
Problem
Conventional resistive elements for semiconductor devices have a large chip size and require multiple bonding wires due to their structural design, which increases complexity and reduces efficiency.
Innovation Solution
A resistive element with a semiconductor substrate, insulating films, and resistive layers, where a relay wire connects the resistive layers to the substrate with an ohmic contact, reducing the number of bonding wires and chip size by using a vertical-type configuration with a resistor between the electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two electrodes are opposed to each other connected on both sides of the top surface of the resistive layer, then electrical connection is achieved, but chip size increases and number of bonding wires increases
Solution Approach 1:
The patent transitions from a planar configuration where both electrodes are on the top surface to a vertical configuration where one electrode is on the top surface and the other is on the bottom surface of the semiconductor substrate. This dimensional change allows electrical connection to be achieved through the thickness of the substrate rather than across the surface area, thereby reducing chip size while maintaining electrical connectivity.
Solution Approach 2:
Instead of placing both electrodes on the same surface (top surface) as in conventional designs, the patent inverts the arrangement by placing one electrode on the top surface and the other on the bottom surface of the substrate. This inversion of the electrode arrangement eliminates the need for two opposing electrodes on the top surface, reducing chip area requirements.
2Reliability
If two electrodes are opposed to each other connected on both sides of the top surface of the resistive layer, then electrical connection is achieved, but number of bonding wires increases
Solution Approach 1:
By moving one electrode to the bottom surface of the substrate, the patent enables electrical connection through the substrate thickness dimension rather than requiring two separate bonding wires on the top surface. This dimensional transition reduces the number of bonding wires from two to one, simplifying the device structure.
Solution Approach 2:
The patent merges the function of two separate bonding wires into a single bonding wire by utilizing the vertical path through the substrate. The single bonding wire connects to the top electrode, and the electrical connection is completed through the substrate to the bottom electrode, thereby combining what would have been two separate connection paths into one.
3Ease of manufacture
If conventional resistive element structure is used, then manufacturing process is established, but chip size is large and manufacturing efficiency is reduced
Solution Approach 1:
The patent modifies the conventional manufacturing process by adding a vertical connection dimension through the substrate. This involves forming a through-substrate via or contact that connects the top electrode to the bottom electrode, transforming a planar manufacturing process into a three-dimensional one. This dimensional addition reduces chip size while maintaining ease of manufacture through standard semiconductor fabrication techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the chip size and number of bonding wires, enhancing manufacturing efficiency and preventing oscillation by minimizing parasitic capacitance and current concentration.
Implementation Method 1
a relay wire deposited on the second insulating film without being in contact with the first electrode, and including a resistive-layer connection terminal electrically connected to the resistive layer and a substrate connection terminal connected to the semiconductor substrate with an ohmic contact
Data Source
AI summary
A resistive element includes: a semiconductor substrate; a first insulating film deposited on the semiconductor substrate; a resistive layer deposited on the first insulating film; a second insulating film deposited to cover the first insulating film and the resistive layer; a first electrode deposited on the second insulating film and electrically connected to the resistive layer; a relay wire deposited on the second insulating film without being in contact with the first electrode, and including a resistive-layer connection terminal electrically connected to the resistive layer and a substrate connection terminal connected to the semiconductor substrate with an ohmic contact; and a second electrode deposited on a bottom side of the semiconductor substrate, wherein a resistor is provided between the first electrode and the second electrode.