Vertical Resistive Memory Device with Charge Trap Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Resistive memory devices face challenges in improving the reliability of program operations due to limitations in maintaining data integrity and resistance state transitions.
Innovation Solution
The resistive memory device incorporates a vertical structure with conductive layers, interlayer insulating layers, a gate insulating layer, a charge trap layer, a channel layer, and a variable resistance layer, where electrons are trapped in the charge trap layer and voltages are applied to manage the resistance state, eliminating the need for negative voltages and enhancing data storage reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional resistive memory structure with top electrode and bottom electrode is used, then data storage is achieved through resistance change, but the reliability of program operation is insufficient
Solution Approach 1:
The memory device is segmented into multiple functional layers including gate insulating layer, charge trap layer, channel layer, and variable resistance layer, each performing specific functions to improve program operation reliability while maintaining manufacturing feasibility
Solution Approach 2:
The invention transitions from a planar two-electrode structure to a vertical multi-layer structure with a hole penetrating through conductive layers, enabling improved program operation reliability through three-dimensional charge trapping and resistance modulation mechanisms
2Ease of operation
If negative voltages are used for resistance state transitions, then programming capability is achieved, but voltage generation complexity increases
Solution Approach 1:
A charge trap layer is introduced as an intermediary between the control gate and the variable resistance layer, enabling resistance state transitions through charge trapping and detrapping mechanisms that eliminate the need for negative voltage generation
Solution Approach 2:
The invention changes the operating parameter from negative voltage application to positive voltage-controlled charge trapping, simplifying the voltage generation system while maintaining full programming capability through controlled electron injection into the charge trap layer
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the reliability of program operations by maintaining data integrity and efficiently transitioning between high and low resistance states, reducing the complexity of voltage generation and enhancing overall performance.
Implementation Method 1
trapping electrons in the charge trap layer of the selected memory cell connected to a selected word line
Data Source
AI summary
A resistive memory device includes: conductive layers and interlayer insulating layers, which are alternatively stacked; a vertical hole vertically penetrating the conductive layers and the interlayer insulating layers; a gate insulating layer disposed over an inner wall of the vertical hole; a charge trap layer disposed over an inner wall of the gate insulating layer; a channel layer disposed over an inner wall of the charge trap layer; and a variable resistance layer disposed over an inner wall of the channel layer.