Vertical Resistor Capacitor Integration on SAC Gate Caps
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Solution Overview
Problem
In semiconductor devices, the integration of resistors and capacitors into ultra-high density integrated circuits is challenging due to the need for thick dielectric layers that cause dimensional changes and electrical shorts, and the use of multiple masks increases manufacturing complexity and cost.
Innovation Solution
A semiconductor structure with resistors and MIM capacitors disposed directly over a self-aligned contact (SAC) cap of a transistor gate, eliminating the need for additional dielectric layers and reducing the number of masks required, allowing for improved MOL process quality and functional enablement of transistors beneath the resistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dielectric layer is disposed between the gate structure and resistors to prevent electrical shorting, then electrical insulation is improved, but the thickness of dielectric layers increases which exacerbates dimensional changes in width between the top and bottom of contacts
Solution Approach 1:
The patent transitions from horizontal planar integration to vertical three-dimensional integration by stacking resistors and capacitors directly on top of the gate structure. This vertical arrangement eliminates the need for thick lateral dielectric layers, reducing dimensional changes during etching while maintaining electrical insulation through the inherent gate oxide and interfacial layers.
Solution Approach 2:
The patent extracts and eliminates the intermediate thick dielectric layer that was previously required between the gate structure and resistors. By directly forming resistors and capacitors on the gate structure, the design removes this unnecessary insulating layer, thereby minimizing etching-induced dimensional changes in contact dimensions.
2Productivity
If resistors are integrated into the semiconductor structure during MOL process flow, then integration density is improved, but transistors under the resistors are rendered non-functional due to blocked electrical connections
Solution Approach 1:
The patent utilizes the vertical dimension by stacking resistors and capacitors on top of the gate structure rather than placing them laterally adjacent to transistors. This vertical stacking allows electrical contacts to access transistor terminals from the sides and bottom without being blocked by resistors, maintaining transistor functionality while achieving high integration density.
Solution Approach 2:
The patent segments the device structure into distinct functional zones: the gate structure with stacked resistors/capacitors forms one segment, while the source/drain regions and their contacts form separate accessible segments. This segmentation allows independent electrical access to transistor terminals without interference from the resistor layer.
3Reliability
If multiple masks are used to form resistors and capacitors in separate process flows, then device functionality is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges the formation of resistors and capacitors into a single integrated process flow that occurs during the MOL stage, rather than requiring separate BEOL process flows. Both structures are formed simultaneously using the same mask patterns and deposition/etching sequences, eliminating the need for multiple additional masks and reducing manufacturing complexity.
Solution Approach 2:
The patent employs universal mask patterns and process steps that serve multiple functions: the same masks used for contact hole formation also define resistor and capacitor geometries. This multi-functionality reduces the total number of masks required while maintaining precise device functionality.
Data Source
AI summary
A semiconductor structure includes a substrate. A gate structure is disposed over the substrate. The gate structure includes: a pair of gate spacers extending generally vertically from the substrate, gate metal disposed between the spacers, and a self-aligned contact (SAC) cap disposed over the gate metal to form a top of the gate structure. A first capacitor plate is disposed directly upon the SAC cap such that no additional layer is disposed between the resistor and SAC cap. An insulator layer and a second capacitor plate are disposed on the first capacitor plate forming a MIM capacitor. A pair of capacitor plate contacts are electrically connected to the first capacitor plate and the second capacitor plate.