Vertical Resistor Structure for Area-Efficient Semiconductor Circuits
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Solution Overview
Problem
In integrated circuits, the physical dimensions of electrical resistors do not scale with smaller nodes, leading to an increased proportion of circuit area dedicated to resistors, which in turn affects the cost and topology of the circuit.
Innovation Solution
A semiconductor device with a resistance element that extends vertically, reducing area requirements, and can be fabricated as part of either frontend of line (FEOL) or backend of line (BEOL) processing without additional mask processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If resistors are fashioned laterally parallel to main surfaces of the carrier, then the resistor structure is simple and compatible with conventional manufacturing, but the area required for the resistor increases the total device size
Solution Approach 1:
The patent applies vertical stacking to transition from lateral (2D) resistor configuration to vertical (3D) configuration. The resistance element extends in the vertical direction through multiple layers including conductive layers and dielectric layers, allowing current to flow vertically rather than laterally. This dimensional change enables high resistance values to be achieved within a small footprint area, directly resolving the contradiction between manufacturing simplicity and area reduction.
2Productivity
If node size is reduced to scale down circuits, then circuit integration density improves, but resistor physical dimensions do not scale and occupy a larger proportion of circuit area
Solution Approach 1:
The vertical stacking architecture allows resistors to scale with node size by extending into the vertical dimension. As node size reduces, the vertical resistance element can maintain or increase its resistance value by adjusting layer thicknesses and materials without increasing lateral footprint. This enables continued scaling of circuit integration density while keeping resistor area proportion controlled.
Solution Approach 2:
The patent employs composite material structures including conductive layers (such as doped polysilicon or metal), dielectric layers (such as silicon nitride or silicon oxide), and intermediate layers with different electrical properties. These composite structures enable precise control of resistance values through material composition and layer thickness, allowing high resistance values in compact vertical configurations that scale with technology nodes.
3Area of stationary object
If additional mask processes are used to create vertical resistance elements, then resistor area is reduced, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges the formation of vertical resistance elements with existing conventional fabrication processes. The stacked structure is created using standard deposition, etching, and doping techniques already employed in CMOS manufacturing. By integrating the vertical resistor formation into the existing process flow rather than adding separate mask steps, the patent achieves area reduction without increasing manufacturing complexity or cost.
Data Source
AI summary
A semiconductor device including a carrier having two main surfaces situated opposite one another, a circuit, having at least one resistance element, in and/or on the carrier, wherein the at least one resistance element has a longitudinal axis extending vertically between the main surfaces of the carrier, and a current limiting circuit configured to limit a current flowing through the resistance element to a value at which it is ensured that an electrical resistance of the resistance element remains substantially unchanged.