Vertical Multilayer Resistor Structure for Stress-Stable Trimming
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Solution Overview
Problem
Existing semiconductor devices with polycrystalline silicon resistors face resistance value fluctuations due to stress from mold resin, limiting design freedom and requiring higher accuracy in trimming circuits.
Innovation Solution
A resistance element formed in multiple wiring layers with a main resistance perpendicular to the semiconductor substrate plane, utilizing conductive layers and vias to minimize stress-induced fluctuations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a polycrystalline silicon resistor is used in the trimming circuit, then the resistance value can be adjusted on a chip-by-chip basis and the manufacturing process is simplified, but the resistance value fluctuates after package molding due to stress from mold resin
Solution Approach 1:
The patent transitions from planar resistors (2D) to three-dimensional stacked vias (3D), changing the resistance direction from in-plane to vertical. This dimensional change allows the resistor to be formed using existing wiring layers without adding process complexity, while the vertical configuration reduces sensitivity to stress from mold resin, thereby maintaining manufacturing simplicity while improving resistance stability.
2Manufacturing precision
If the location of polycrystalline silicon resistor is restricted to reduce stress, then resistance fluctuation is reduced, but design freedom is degraded
Solution Approach 1:
The stacked via structure serves multiple functions: it provides resistance in the vertical direction, utilizes existing wiring layers for formation, and reduces stress sensitivity. This multi-functionality allows the same structure to be implemented anywhere on the chip without location-specific design constraints, thereby achieving both resistance stability and design freedom.
3Measurement precision
If higher accuracy is required in trimming circuits, then the coefficient of fluctuation in resistance must be lowered, but existing polycrystalline silicon resistors cannot achieve below ±0.5% fluctuation
Solution Approach 1:
The patent changes the physical configuration parameter from planar to vertical stacked structure, and changes the material composition by using different conductive materials in different wiring layers. These parameter changes result in a resistance structure that is less sensitive to stress, achieving a coefficient of fluctuation below 0.2% and enabling higher trimming circuit accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves low resistance fluctuations post-package molding, enhancing design freedom and accuracy, with a coefficient of fluctuation reduced to below 0.2%.
Implementation Method 1
This fluctuation in resistance value is caused by a change in shape, a piezoelectric effect, or the like as the result of a resistance element (polycrystalline silicon resistor) on a silicon chip being subjected to stress from mold resin.
Data Source
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AI summary
A polycrystalline silicon resistor is large in coefficient of fluctuation in resistance between before and after the completion of a package molding process. To enable highly accurate trimming, it is desired to implement a resistor that is hardly subjected to stress produced in a substrate during a package molding process. A resistance element is formed of a plurality of wiring layers and has a repetitive pattern of a first conductive layer formed in a first wiring layer, a second conductive layer formed in a second wiring layer, and an interlayer conductive layer coupling the first conductive layer and the second conductive layer together.