3D Vertical Resistor Structure for High Integration Density
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Solution Overview
Problem
Semiconductor devices face challenges in achieving the required resistance values for resistors without increasing the area occupied within the substrate, which can deteriorate high integration due to the use of conductive gate layers with low resistance.
Innovation Solution
The semiconductor device employs alternately stacked first and second material layers with through holes and trenches to form resistive layers, allowing for the creation of resistors with specific resistance regions, thereby maintaining resistance values without expanding the substrate area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the resistor is formed by using the gate layer with low resistance conductive material, then the resistance value of the resistor cannot be maintained to be larger than that of the gate layer
Solution Approach 1:
The patent transitions from 2D planar resistor formation to 3D vertical stacking by forming first and second through holes that extend through multiple material layers stacked on the gate layer. This vertical dimension allows the resistor to achieve higher resistance values without increasing the planar area, as the current must traverse through multiple layers and interfaces, effectively solving the contradiction between maintaining resistance value and ease of manufacture.
Solution Approach 2:
The patent embeds the resistor structure within the existing gate layer architecture by forming through holes that pass through the gate layer and stacking additional material layers around them. The resistor is nested within the vertical stack of material layers, utilizing the gate layer as a foundation rather than trying to form the resistor directly from the gate layer, thus resolving the manufacturing difficulty while maintaining reliability.
2Reliability
If the length of the resistor in a 2D plane is increased to achieve larger resistance value, then the area occupied by the resistor is increased
Solution Approach 1:
The patent resolves this contradiction by moving the resistor design from 2D planar extension to 3D vertical stacking. The first and second through holes extend vertically through multiple material layers, allowing the resistor to achieve high resistance values through the vertical path length rather than horizontal area expansion. This maintains high integration density while achieving the required resistance values.
Solution Approach 2:
The patent divides the resistor into multiple segments distributed across different material layers. Instead of forming a single long resistor in one layer, the resistor is segmented into portions within the gate layer, first material layers, and second material layers, connected through the through holes. This segmentation allows the total resistance to be achieved through vertical stacking rather than horizontal extension.
3Difficulty of detecting and measuring
If the gate layer is formed of conductive material with low resistance to improve conductivity, then the resistance value of the resistor formed from the gate layer becomes too low
Solution Approach 1:
The patent introduces additional material layers (first and second material layers) as intermediaries between the gate layer and the external circuitry. These intermediate layers have higher resistance than the gate layer and are positioned in the path of current flow through the through holes. This allows the gate layer to maintain its low-resistance conductive material for good electrical connection, while the intermediate material layers provide the necessary resistance for the resistor function, resolving the contradiction between measuring resistance and achieving appropriate resistance values.
Data Source
AI summary
Disclosed is a semiconductor device and a method of manufacturing the same. The semiconductor device includes first material layers and second material layers alternately stacked on a first conductive layer. Through holes, each through holes including a first through region, second through region and trench, wherein the first and second through regions pass through the first and second material layers, and the trench is formed in the first conductive layer to connect the first through region and the second through region. Resistive layers, each resistive layer including a first region are disposed in the first through region, a second region disposed in the second through region, and a third region disposed in the trench.