Vertical Ribbon Inductor on Semiconductor Substrate
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Solution Overview
Problem
Conventional inductors in silicon-based integrated circuits face performance limitations due to capacitive coupling and low self-resonant frequency, primarily because their windings lie directly on the silicon substrate or silicon oxide layer, which degrades the quality factor (Q factor) and self-resonant frequency.
Innovation Solution
The development of vertical ribbon inductors with a high aspect ratio (height-to-width ratio greater than 1) freestanding electrical conductors, arranged in a serpentine path on the semiconductor substrate, reduces surface current density and adverse mutual inductance, thereby minimizing capacitive coupling and enhancing the Q factor and self-resonant frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional inductor windings are placed directly on silicon substrate or silicon oxide layer, then manufacturing is simple, but Q factor is degraded and self-resonant frequency is lowered due to capacitive coupling
Solution Approach 1:
The patent transitions from planar windings lying flat on the substrate to vertical ribbons standing perpendicular to the substrate. This dimensional change from 2D to 3D configuration reduces the surface area of the windings that are in proximity to the substrate, thereby minimizing capacitive coupling while maintaining manufacturing feasibility through vertical deposition techniques.
Solution Approach 2:
The patent introduces an air gap or vacuum space between the vertical ribbon windings and the silicon substrate. This intermediary space acts as a dielectric barrier that significantly reduces capacitive coupling between the windings and the substrate, thereby improving the Q factor without adding complex insulating layers directly between the windings and substrate.
2Device complexity
If conventional inductor windings are placed directly on silicon substrate, then device structure is simple, but self-resonant frequency is lowered due to capacitive coupling
Solution Approach 1:
By standing the windings vertically rather than laying them flat, the patent reduces the effective capacitive area between the windings and substrate. This dimensional transformation maintains structural simplicity while significantly lowering parasitic capacitance, thereby raising the self-resonant frequency of the inductor.
3Reliability
If vertical ribbon inductors with high aspect ratio are used, then Q factor and self-resonant frequency are enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent optimizes the aspect ratio (height-to-width ratio) of the vertical ribbons to be greater than 1. This parameter change allows the ribbons to achieve sufficient height to reduce capacitive coupling while maintaining manufacturability through standard semiconductor fabrication processes. The specific aspect ratio range balances performance improvement with manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in higher Q factor values and self-resonant frequencies for inductors, reducing manufacturing complexity and costs compared to spiral inductors, while maintaining adequate DC resistance and operational reliability.
Implementation Method 1
the presence of any type of dielectric layers between or beneath the windings generally results in some amount of capacitive coupling. Such capacitive coupling generally degrades the Q factor and lowers the self-resonant frequency of the inductor
Implementation Method 2
reduces surface current density and adverse mutual inductance, thereby minimizing capacitive coupling
Implementation Method 3
reduces surface current density and adverse mutual inductance, thereby minimizing capacitive coupling
Data Source
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AI summary
A method of making a semiconductor device and devices thereof are provided. The semiconductor device (100) includes a semiconductor substrate (102) having opposing first and second surfaces (102a, 102b). The device further includes a planar inductor element (104) disposed on said first surface. The planar inductive element (103) comprises a freestanding electrical conductor extending along a meandering path and defining a plurality of windings (104), where the electrical conductor has a width and a height, and where a height-to-width (HW) ratio is substantially greater than 1.