Vertical Routing Structure for Dense Semiconductor Control Layouts
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Solution Overview
Problem
High aspect ratio semiconductor devices occupy less substrate surface area but require multiple controlling devices for sophisticated control, leading to increased surface area usage and reduced controllability.
Innovation Solution
A semiconductor device with a vertical routing structure is developed, where vias and metal layers are formed to overlap and extend in different directions, allowing for efficient reduction of substrate surface area occupied by controlling devices while enhancing controllability and complexity of control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If high aspect ratio device structure is used, then substrate surface area is reduced, but controllability is reduced due to scattering of control circuit components
Solution Approach 1:
The patent transitions from planar routing to vertical routing by forming vias that extend in the depth direction (z-axis) through multiple interlayer dielectric layers. This dimensional change allows control signals to be routed vertically rather than horizontally, reducing the substrate surface area occupied by control circuits while maintaining full controllability of the light emitting element
2Adaptability or versatility
If multiple controlling devices are used for sophisticated control, then controllability is enhanced, but substrate surface area occupied increases
Solution Approach 1:
The vertical routing structure enables multiple control signals to be stacked vertically through different metal layers and vias, allowing sophisticated control of the light emitting element without requiring multiple controlling devices to be placed side-by-side on the substrate surface
Solution Approach 2:
The patent implements a nested structure where multiple metal layers (first, second, third metal layers) and interlayer dielectric layers are stacked vertically, with vias penetrating through these layers. This nested arrangement allows multiple control functions to be integrated in the vertical dimension, reducing the horizontal footprint on the substrate
Data Source
AI summary
A method includes forming a transistor having source and drain regions. The following are formed on the source/drain region: a first via, a first metal layer extending along a first direction on the first via, a second via overlapping the first via on the first metal layer, and a second metal extending along a second direction different from the first direction on the second via; and the following are formed on the drain/source region: a third via, a third metal layer on the third via, a fourth via overlapping the third via over the third metal layer, and a controlled device at a same height level as the second metal layer on the third metal layer.