Vertical Routing Structure for Compact Semiconductor Control
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Solution Overview
Problem
High aspect ratio semiconductor devices occupy less substrate surface area but require multiple controlling devices for sophisticated control, leading to increased surface area usage and reduced controllability.
Innovation Solution
A semiconductor device with a vertical routing structure is developed, where vias and metal layers are formed to overlap and extend in different directions, allowing for efficient use of substrate space and enhanced controllability by integrating multiple controlling devices in a compact vertical structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If high aspect ratio device structure is adopted to reduce substrate surface area, then device density is improved, but multiple controlling devices are required which increases surface area usage
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional vertical routing structure. Vias extend vertically through multiple interlayer dielectric layers, allowing control signals to reach the high aspect ratio device from below rather than requiring lateral placement of controlling devices on the substrate surface. This vertical dimension enables compact integration while maintaining full controllability.
Solution Approach 2:
The controlling devices are nested within the vertical stack structure, with vias and metal layers embedded within interlayer dielectric layers. The control circuit components are integrated into the same vertical column as the high aspect ratio device, creating a compact nested arrangement that minimizes lateral footprint while providing sophisticated control.
2Adaptability or versatility
If multiple controlling devices are added to achieve sophisticated control, then controllability is improved, but substrate surface area occupied increases
Solution Approach 1:
The patent utilizes the vertical dimension through multiple stacked interlayer dielectric layers and vias to route control signals. Instead of spreading controlling devices laterally across the substrate surface, the structure stacks control pathways vertically, allowing multiple control lines to occupy the same lateral footprint while maintaining sophisticated controllability.
Solution Approach 2:
Multiple control functions are merged into a single vertical routing column. The vias and metal layers are combined to form an integrated control pathway that delivers multiple control signals to the high aspect ratio device from a compact base structure, merging what would traditionally require separate lateral placements into a unified vertical structure.
Data Source
AI summary
A method includes forming a transistor having source and drain regions. The following are formed on the source/drain region: a first via, a first metal layer extending along a first direction on the first via, a second via overlapping the first via on the first metal layer, and a second metal extending along a second direction different from the first direction on the second via; and the following are formed on the drain/source region: a third via, a third metal layer on the third via, a fourth via overlapping the third via over the third metal layer, and a controlled device at a same height level as the second metal layer on the third metal layer.