Vertical Routing of Stacked Transistor Logic Gates
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Solution Overview
Problem
Conventional methods for scaling logic standard cells in semiconductor devices face challenges as they reach the limits of two-dimensional fabrication, particularly at single-digit nanometer nodes, where further reduction in track height and contacted gate pitch is difficult, and traditional scaling techniques are exhausted.
Innovation Solution
The method involves vertically routing floating stacked transistors and source/drain electrodes, allowing current to flow between stacked logic gates, enabling area-scale enhancement through a layered deck configuration, where power is supplied via buried rails and current flows vertically between decks, reducing the need for multiple tracks and increasing scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional two-dimensional scaling methods are used to increase transistor density, then transistor count per unit area increases, but further scaling becomes difficult at single-digit nanometer nodes due to limits in track height and contacted gate pitch reduction
Solution Approach 1:
The patent transitions from two-dimensional planar transistor arrangement to three-dimensional vertical stacking of transistors. Multiple transistor decks are stacked vertically with current flowing between decks through vertical connections, enabling continued scaling beyond the limits of 2D fabrication while simplifying the manufacturing process by using standardized vertical stacking techniques.
2Quantity of substance
If more transistors are stacked vertically to increase density, then transistor density improves, but device height increases
Solution Approach 1:
Multiple transistor decks are merged vertically into a compact stacked structure where shared source/drain regions and interconnect structures serve multiple transistors. The vertical stacking with shared infrastructure reduces the overall height increase compared to separate vertical transistors, achieving high density while controlling device height.
3Area of stationary object
If vertically stacked transistor decks are implemented, then area scaling is achieved, but routing complexity between decks increases
Solution Approach 1:
The vertical interconnect structures serve multiple functions: they provide electrical connections between stacked transistor decks, act as shared source/drain regions for adjacent transistors, and function as interconnect pathways for signal and power distribution. This multi-functionality reduces routing complexity by eliminating the need for separate dedicated connection structures.
Data Source
AI summary
A semiconductor device includes: a substrate having a surface, the surface being planar; a first logic gate provided on the substrate and comprising a first field effect transistor (FET) having a first channel, and a first pair of source-drain regions; a second logic gate stacked over the first logic gate along a vertical direction perpendicular to the surface of the substrate, the second logic gate comprising a second FET having a second channel, and a second pair of source-drain regions; and a contact electrically connecting a source-drain region of the first FET to a source-drain region of the second FET such that at least a portion of current flowing between the first and second logic gate will flow along said vertical direction.