Vertical RRAM Interconnect Structure for Higher Chip Density
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Solution Overview
Problem
The challenge in semiconductor integrated circuits is to increase device density while managing the complexity of processing and manufacturing, particularly in integrating resistive random access memory (RRAM) devices without significant modifications to existing fabrication processes.
Innovation Solution
A vertical RRAM device is integrated as a metal-insulator-metal (MIM) fused device between metal layers, utilizing indium-gallium-zinc-oxide (IGZO) channels and a gate-all-around structure, with nanostructure transistors patterned using photolithography and self-aligned processes to enhance density and reduce passive device area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device density is increased by scaling down geometry size, then production efficiency and cost are improved, but processing and manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar 2D device layout to vertical 3D stacked architecture, where RRAM devices are integrated between metal layers in the vertical dimension. This allows increased device density without further scaling lateral geometry dimensions, thereby avoiding the processing complexity issues associated with continued miniaturization while maintaining high productivity
Solution Approach 2:
The RRAM device is nested within the existing metal layer interconnect structure, with the resistive switch positioned between metal layers. This nested integration allows the memory device to utilize the existing fabrication infrastructure without requiring significant modifications to the established manufacturing process, thus improving productivity without substantially increasing processing complexity
2Ease of manufacture
If RRAM devices are integrated into existing fabrication processes, then manufacturing complexity is reduced, but device density and performance may be compromised
Solution Approach 1:
By moving to vertical stacking in the third dimension, the patent achieves high device density without requiring complex lateral patterning processes. The vertical integration approach maintains compatibility with existing planar fabrication processes while dramatically increasing the number of devices per chip area, thus improving productivity without sacrificing ease of manufacture
Solution Approach 2:
The fabrication process is designed to be universal, using the same metal deposition and patterning tools for both the interconnect structure and the RRAM device electrodes. The resistive switch integration utilizes standard thin-film deposition techniques already present in modern CMOS fabrication, allowing high device density to be achieved without requiring specialized manufacturing equipment or processes
Data Source
AI summary
A device includes: a device layer; and an interconnect structure on the device layer, the interconnect structure including a resistive random access memory (RRAM) device. The RRAM device includes: an electrode layer above the device layer; an oxide semiconductor layer on the electrode layer; a gate structure that wraps around the oxide semiconductor layer; an insulating layer on the gate structure; and a resistor. The resistor includes: a bottom electrode on the oxide semiconductor layer; a dielectric layer on the bottom electrode; and a top electrode on the dielectric layer.