Vertical RRAM Cell Structure for Area Saving and Electrode Isolation
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Solution Overview
Problem
Conventional resistive random-access memory (RRAM) devices face challenges in optimizing memory cell area usage and preventing damage to resistive materials, as well as avoiding connections between top and bottom electrodes.
Innovation Solution
The RRAM device is designed with vertical resistance layers sandwiched by a top electrode island and bottom electrodes, where the resistive material is sandwiched between the sidewalls of these electrodes, forming a U-shape cross-sectional profile to save area and prevent damage, and a method involving a bottom electrode line, inter-dielectric layer, and vertical top electrode is used to create these structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional RRAM device structure is used, then the device can store data using variable resistance of transition metal oxide, but the memory cell area is large and top electrode may connect to bottom electrode through metal structure
Solution Approach 1:
The patent transitions from a planar horizontal electrode arrangement to a vertical three-dimensional structure. The bottom electrode extends vertically to form a bottom electrode line, and the top electrode forms a vertical column, with resistive material sandwiched between them in the vertical dimension. This dimensional change reduces the horizontal footprint and eliminates metal structure interference between electrodes.
Solution Approach 2:
The patent segments the electrode structure into distinct vertical components: bottom electrode lines formed on the substrate, inter-dielectric layers separating these lines, and vertical top electrodes positioned above specific bottom electrode regions. This segmentation creates isolated vertical channels that prevent unintended electrical connections while maintaining compact area.
2Area of stationary object
If vertical electrode structure is implemented, then memory cell area is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary patterning actions by forming bottom electrode lines and inter-dielectric layer structures before depositing the resistive material and top electrodes. The bottom electrode lines are pre-formed with precise positioning, and inter-dielectric layers are pre-deposited to define vertical channels. This preliminary structuring simplifies subsequent steps by providing pre-defined templates for material deposition.
Solution Approach 2:
The patent implements a nested structure where the resistive material is confined within vertical channels defined by bottom electrode lines and inter-dielectric layers. The top electrode then fills and caps these channels, creating a nested arrangement where each layer is positioned within the structural framework established by previous layers. This nesting approach organizes complex multi-layer fabrication into sequential, manageable steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively saves memory cell area, prevents resistive material damage, and avoids connections between electrodes, enhancing the reliability and integration of RRAM devices with logic processes.
Implementation Method 1
The operating theory is to use the variable resistance of the transition metal oxide. The applied bias voltage changes to induce different resistance values
Data Source
AI summary
A RRAM (resistive random-access memory) device includes a bottom electrode line, a top electrode island and a resistive material. The bottom electrode line is directly on a first metal structure. The top electrode island is disposed beside the bottom electrode line. The resistive material is sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island. The present invention also provides a method of forming said RRAM device.