Vertical and Saddle Fin Transistor Integration via Recessed Trench Isolation
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Solution Overview
Problem
Current semiconductor device fabrication methods lack effective integration of vertical field-effect transistors and saddle fin-type field-effect transistors into integrated circuits, requiring improved structural and fabrication techniques to enhance device performance.
Innovation Solution
The integration of trench isolation in a substrate to define device regions, with a saddle fin-type field-effect transistor and a vertical field-effect transistor, where the first semiconductor fin has a channel recess and a gate electrode positioned within, and the second semiconductor fin has a recessed trench isolation to accommodate different gate electrode thicknesses, allowing for efficient co-fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If vertical field-effect transistors and saddle fin-type field-effect transistors are integrated using conventional fabrication methods, then device functionality is achieved, but manufacturing precision and device performance are insufficient due to inability to accommodate different gate electrode thicknesses
Solution Approach 1:
The patent applies local quality by creating different trench isolation depths in different device regions. The first trench isolation has a first depth while the second trench isolation has a second depth greater than the first depth. This allows the first gate electrode and second gate electrode to have different thicknesses while maintaining proper alignment and electrical characteristics for each transistor type, thereby achieving high manufacturing precision without excessive device complexity.
2Reliability
If different gate electrode thicknesses are used for vertical and saddle fin-type transistors, then device performance is optimized, but fabrication complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-forming trench isolations with different depths before depositing the gate electrodes. The first trench isolation is formed with a first depth and the second trench isolation is formed with a second depth greater than the first depth. This preliminary structuring enables subsequent gate electrode deposition to naturally accommodate different thicknesses without requiring complex post-processing or multiple deposition steps, thus optimizing device performance while maintaining ease of manufacture.
3Adaptability or versatility
If trench isolation surfaces are at different levels, then different gate electrode thicknesses are accommodated, but edge effects increase
Solution Approach 1:
The patent applies the nesting principle by placing the first gate electrode within the first trench isolation and the second gate electrode within the second trench isolation, where the deeper second trench isolation contains the second gate electrode of greater thickness. This nested arrangement allows different gate electrode thicknesses to be accommodated while the trench isolations provide confining structures that minimize edge effects by containing the electric fields within defined regions, thus achieving adaptability without significant harmful edge effects.
Data Source
AI summary
Structures for the integration of a vertical field-effect transistor and a saddle fin-type field-effect transistor into an integrated circuit, as well as methods of integrating a vertical field-effect transistor and a saddle fin-type field-effect transistor into an integrated circuit. A trench isolation is formed in a substrate that defines a first device region and a second device region. A first semiconductor fin is formed that projects from the first device region and a second semiconductor fin is formed that projects from the second device region. A vertical field-effect transistor is formed using the first semiconductor fin, and a saddle fin-type field-effect transistor is formed using the second semiconductor fin. A top surface of the trench isolation in the second device region adjacent to the second semiconductor fin is recessed relative to the top surface of the trench isolation in the first device region adjacent to the first semiconductor fin.