Vertical Junction Schottky Diode GaN HEMT Integration
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Solution Overview
Problem
Gallium-Nitride (GaN) microwave monolithic integrated circuit (MMIC) high-electron-mobility-transistor (HEMT) technology faces issues with excessive parasitic capacitance and resistance in its lateral junction Schottky diodes, leading to lower operation speed, higher power consumption, and larger physical size, limiting its performance in high-voltage and high-temperature applications.
Innovation Solution
The integration of vertical junction Schottky diodes within a new mesa structure, which minimizes parasitic capacitance and resistance, and physical size, by using a specific sequence of semiconductor layers and etching processes, allowing for the fabrication of both high electron mobility transistors (HEMTs) and Schottky diodes in a single integrated group III nitride structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If lateral junction Schottky diodes are used in GaN HEMT technology, then the device can be fabricated using existing processes, but excessive parasitic capacitance and resistance occur leading to lower operation speed and higher power consumption
Solution Approach 1:
The patent transitions from a lateral junction structure to a vertical junction structure for the Schottky diode. This dimensional change allows the diode junction to be formed vertically through the semiconductor layers rather than laterally within the plane, fundamentally altering the current path and reducing parasitic effects while maintaining compatibility with existing GaN HEMT fabrication processes
2Ease of manufacture
If lateral junction Schottky diodes are used, then fabrication is simplified, but parasitic resistance increases leading to larger physical size
Solution Approach 1:
By changing from lateral to vertical junction configuration, the current flows vertically through the semiconductor layers rather than laterally across the device structure. This vertical current path significantly reduces the effective resistance and allows for a more compact device footprint while maintaining the same current handling capability
3Adaptability or versatility
If lateral junction Schottky diodes are used, then device integration is achieved, but parasitic capacitance increases leading to higher power consumption
Solution Approach 1:
The vertical junction structure reduces the overlap area between charged regions compared to the lateral structure, thereby reducing parasitic capacitance. This reduction in capacitance directly lowers the power consumption during switching operations while maintaining full integration capability with GaN HEMT circuits
Solution Approach 2:
The patent modifies the structural parameters of the Schottky diode by changing from lateral to vertical junction configuration. This parameter change fundamentally alters the electrical characteristics, reducing parasitic capacitance and resistance, and improving overall device performance in integrated circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a GaN Schottky diode with 75% less parasitic resistance and 80% less parasitic capacitance compared to lateral diodes, leading to a 20 times improvement in the RC time constant, enhancing the performance and efficiency of GaN HEMTs in digital, analog, or mixed-mode circuits.
Implementation Method 1
Schottky diodes are semiconductor diodes with a low forward voltage drop and a very fast switching action
Data Source
AI summary
A process for fabricating an integrated group III nitride structure comprising high electron mobility transistors (HEMTs) and Schottky diodes, and the resulting structure, are disclosed. Integration of vertical junction Schottky diodes is enabled, and the parasitic capacitance and resistance as well as the physical size of the diode are minimized. A process for fabricating an integrated group III nitride structure comprising double-heterostructure field effect transistors (DHFETs) and Schottky diodes and the resulting structure are also disclosed.


