Vertical S/D Contact Structure for Low-Resistance GAA Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of multi-gate devices in semiconductor manufacturing is challenging due to increased complexity, and existing methods for scaling down semiconductor IC dimensions do not effectively address the need for improved gate control and reduced short-channel effects while maintaining low power consumption and cost efficiency.
Innovation Solution
The method involves forming a gate-all-around transistor structure with nanostructures and source/drain contact structures that have a large contact area, achieved through advanced photolithography and self-aligned processes, including double-patterning or multi-patterning techniques, to reduce resistance and improve performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-gate devices are integrated to improve gate control and reduce short-channel effects, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The device is segmented into distinct functional regions including source region, drain region, channel region, and gate regions positioned at different heights. This segmentation allows each region to be optimized independently for its specific function while simplifying the overall manufacturing process by breaking down the complex multi-gate structure into manageable segments that can be formed through sequential processing steps.
Solution Approach 2:
The invention introduces vertical dimensionality by positioning gate structures at different heights relative to the substrate. The first gate structure is positioned at a first height and the second gate structure at a second height, creating a three-dimensional multi-gate configuration that enhances gate control over the channel without requiring planar scaling, thereby improving performance while managing manufacturing complexity through vertical integration.
2Productivity
If device dimensions are scaled down to improve production efficiency and lower costs, then productivity is improved, but manufacturing complexity increases
Solution Approach 1:
Instead of continuing to scale down planar dimensions which increases manufacturing complexity, the invention transitions to vertical integration by forming gate structures at different heights. This dimensional transition allows maintaining larger lateral feature sizes that are easier to manufacture while achieving higher device density and performance through the vertical stacking of source, drain, channel, and multi-level gate structures.
Solution Approach 2:
The device structure is divided into discrete segments (source, drain, channel, and multiple gate structures) that can be formed through separate, standardized processing steps. This segmentation enables modular manufacturing where each component can be optimized and fabricated independently, improving production efficiency while managing the complexity of the overall device architecture.
3Reliability
If contact area is increased to reduce resistance, then electrical conductivity is improved, but device area increases
Solution Approach 1:
The contact structure extends in the vertical dimension by forming a conductive path from the substrate through intermediate dielectric layers to the surface. This vertical extension increases the contact area and reduces resistance without requiring a larger lateral footprint, thereby improving electrical conductivity while maintaining a compact device area.
Data Source
AI summary
Semiconductor structures and methods for manufacturing the same are provided. A semiconductor device structure is provided. The semiconductor structure includes a plurality of first nanostructures formed over a substrate, and a gate structure formed over the first nanostructures. The semiconductor structure includes a source/drain (S/D) structure formed adjacent to the gate structure, and a silicide layer formed on a sidewall surface of the S/D structure. The semiconductor structure also includes an S/D contact structure formed over the silicide layer, and the S/D contact structure extends from a first position to a second position The first position is higher than the top surface of the gate structure, and the second position is below the bottommost nanostructure.