Vertical Select Transistors for Semiconductor Memory Integration
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Solution Overview
Problem
The miniaturization of semiconductor memory devices is hindered by the larger size of select transistors relative to memory cells, leading to increased occupied area due to the need for maintaining breakdown voltage characteristics.
Innovation Solution
The semiconductor memory device incorporates a control circuit with vertical select transistors arranged in a matrix configuration, reducing the area occupied by each select transistor and allowing for more efficient integration by forming column and row control circuits below the memory cell array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the select transistor is miniaturized to match memory cell scaling, then the occupied area of the select transistor decreases, but the breakdown voltage characteristics deteriorate
Solution Approach 1:
The select transistor is transformed from a planar configuration to a three-dimensional vertical configuration. The active region extends vertically through multiple layers with gate electrodes positioned at different heights, allowing the transistor to achieve the necessary breakdown voltage characteristics in the vertical dimension while occupying minimal planar area. This dimensional transformation resolves the contradiction by decoupling the area constraint from the voltage requirement.
Solution Approach 2:
Multiple gate electrodes are nested vertically around the active region, with each gate electrode positioned at a different height. This nested structure allows the select transistor to control multiple memory cell layers simultaneously while maintaining compact footprint. The nested arrangement of gates enables the transistor to achieve high breakdown voltage capability without increasing planar occupation area.
2Reliability
If the select transistor maintains conventional planar configuration, then the breakdown voltage characteristics are maintained, but the occupied area increases relative to memory cell size
Solution Approach 1:
The invention transitions from two-dimensional planar transistor layout to three-dimensional vertical transistor structure. The active region extends vertically through the substrate with gate electrodes arranged at different heights, enabling the select transistor to maintain breakdown voltage characteristics while occupying significantly reduced planar area compared to conventional planar configurations.
Solution Approach 2:
The vertical select transistor structure enables dynamic control of multiple memory cell layers through stacked gate electrodes. By applying voltages to different gate electrodes at different heights, the transistor can selectively control access to specific memory layers, providing dynamic functionality that reduces the need for additional transistors and further decreases occupied area.
Data Source
AI summary
A memory cell array comprises first wiring lines, second wiring lines, and memory cells disposed at intersections thereof. A control circuit comprises a first power-supply line supplying a first voltage to selected ones of the first or second wiring lines, and first selection circuits connected between the first or second wiring lines and the first power-supply line, each first selection circuit comprising first and second transistors connected in series. The first selection circuits arranged along a first direction are connected to a first selection line. The first selection circuits arranged along a second direction perpendicular to the first direction are commonly connected to a second selection line. The first and second transistors each comprise a columnar semiconductor portion extending in a direction perpendicular to a semiconductor substrate, a gate-insulating film in contact with a side surface of the columnar semiconductor, and a gate electrode in contact with the gate-insulating film.