3D Memory Cell Array With Vertical Selection Diode
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Solution Overview
Problem
The challenge in memory cell technology is to reduce the size of memory cells for increased density while ensuring that the selection diode can enable a high current flow through the cell, which is essential for reading and writing operations in resistively switching memory cells like PCRAM.
Innovation Solution
The solution involves forming an array of memory cells with selection diodes that include a p+ doped anode and n-doped cathode, where the diodes are integrated with phase change material, allowing for efficient current flow by structuring the selection lines and trenches in a way that maximizes conductivity and minimizes area, enabling high current transmission while maintaining a compact design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of memory cells is reduced to increase density, then memory cell density is improved, but the selection diode's ability to enable high current flow deteriorates
Solution Approach 1:
The patent transitions from planar 2D memory cell layout to a 3D vertical structure by forming trenches through the substrate and creating vertically stacked diode structures. The selection diode is formed with a p-type region in the substrate and an n-type region extending vertically into the trench, enabling high current flow through the vertical dimension while reducing the horizontal footprint of each memory cell.
Solution Approach 2:
The patent implements nesting by placing the n-type doped region inside the trench that extends into the substrate, with the p-type doped region forming the base. The memory element is then formed within the trench structure, creating a nested configuration where multiple functional regions are contained within a compact vertical space, achieving high density without compromising current flow capability.
2Reliability
If the selection diode is made larger to enable high current flow, then current flow capability is improved, but memory cell area increases
Solution Approach 1:
The patent resolves this contradiction by moving the current flow path into the vertical dimension through trench formation. The n-type region extends vertically into the substrate trench, creating a high-current pathway that does not occupy additional horizontal area. This vertical current channel enables sufficient current flow for switching operations while maintaining a compact lateral footprint for each memory cell.
Solution Approach 2:
The patent applies local quality by concentrating the high-current capability specifically in the vertical trench region where the p-n junction is formed, while the surrounding horizontal area remains compact. The doped regions are localized to specific zones within the trench structure, providing high current flow capability exactly where needed without expanding the overall memory cell area.
3Power
If high current is sent through the switching active material to change its state, then switching performance is improved, but the selection diode must be larger to handle the current
Solution Approach 1:
The patent enables high switching power through the vertical trench structure. The p-n junction diode formed in the vertical trench provides a low-resistance current path that can handle high switching currents without requiring large horizontal area. The vertical configuration of the doped regions creates an efficient current channel that supports high-power switching operations in a compact footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the size of memory cells, allowing for higher memory cell density while ensuring that each cell can handle the necessary current for switching operations, thereby enhancing the performance and efficiency of resistively switching memory technologies.
Implementation Method 1
selection diodes that include a p+ doped anode and n-doped cathode
Implementation Method 2
a high current is sent through the volume of switching active material in order to heat and subsequently change the material from a one state to the other
Implementation Method 3
phase change random access memory (PCRAM), the information is stored in a volume of switching active material, wherein the switching active material may switch between two states
Data Source
AI summary
An integrated circuit including an array of memory cells and method. In one embodiment, each memory cell includes a resistively switching memory element and a selection diode for selecting one cell from the plurality of memory cells. The memory element is coupled with its top to a first selection line and with its bottom side to the selection diode, the diode further being coupled to the bottom side of a second selection line.