Vertical Selection Transistors with Shared Channel for Resistive Memory
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Solution Overview
Problem
Conventional resistive memory devices face challenges in scaling down memory cell size due to issues with current drivability and punch-through current leakage as feature size shrinks, limiting device density and efficiency.
Innovation Solution
A novel memory device design featuring an array of vertical selection transistors sharing a common channel, which increases channel width and length, reducing cell size to 4F^2 while minimizing current leakage and enhancing current drivability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional selection transistors are used in resistive memory devices, then faster random access time is achieved, but memory cell size increases reducing device density
Solution Approach 1:
The patent transitions from planar (2D) transistor channels to vertical (3D) trench-based channels. The channel extends vertically through the trench depth rather than horizontally in the plane, enabling increased channel width and length without increasing the lateral footprint of the memory cell. This dimensional change allows maintaining fast transistor switching while reducing cell area to 4F².
Solution Approach 2:
Multiple drain regions are formed within the vertical trench structure, with each drain region associated with a memory element. The vertical channel accommodates multiple active regions nested along its length, allowing multiple memory cells to share common source and drain structures, thereby reducing overall cell size while maintaining individual cell functionality.
2Area of stationary object
If feature size is scaled down to reduce memory cell size, then device density increases, but current drivability decreases and punch-through current leakage increases
Solution Approach 1:
By moving to vertical channels in trenches, the patent increases both channel width and channel length independently of the lateral feature size F. The channel width can be optimized for current drivability while the channel length (trench depth) provides sufficient gate control to prevent punch-through leakage, even as the lateral footprint shrinks to 4F².
Solution Approach 2:
The patent changes the geometric parameters of the transistor channel by forming vertical trenches with controlled depth and width. This allows independent optimization of channel width (for current drivability) and channel length (for leakage control) without being constrained by the lithographic feature size, thereby maintaining reliability while scaling down cell area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves smaller memory cell size with reduced current leakage and increased current drivability, enabling more efficient and dense resistive memory devices.
Implementation Method 1
When a voltage is applied to one of the gate electrodes, an electric field is induced across the gate dielectric layer to modulate the conductance of a respective one of the common channels
Implementation Method 2
The resistive memory element of Phase Change Random Access Memory (PCRAM) may comprise a phase change chalcogenide compound, which can switch between a resistive amorphous phase and a conductive crystalline phase
Implementation Method 3
The resistive memory element of Conductive Bridging Random Access Memory (CBRAM) relies on the statistical bridging of metal rich precipitates therein for its switching mechanism
Data Source
AI summary
The present invention relates to resistive memory devices incorporating therein vertical selection transistors and methods for making the same. A memory device comprises a semiconductor substrate having a first type conductivity and a plurality of parallel trenches therein; a plurality of parallel common source lines having a second type conductivity opposite to the first type conductivity formed in the trench bottoms; a plurality of parallel gate electrodes formed on the trench sidewalls with a gate dielectric layer interposed therebetween, the gate electrodes being lower in height than the trench sidewalls; and a plurality of drain regions having the second type conductivity formed in top regions of the trench sidewalls, at least two of the drain regions being formed in each of the trench sidewalls and sharing a respective common channel formed in the each of the trench sidewalls and a respective one of the source lines.