Vertical Semiconductor Channel Crystallization for Low Resistance Contacts
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Solution Overview
Problem
Current semiconductor technologies face challenges in achieving low resistance source-level contacts for vertical semiconductor channels in three-dimensional memory devices, which are crucial for efficient memory operations.
Innovation Solution
A method involving the formation of a sacrificial layer, alternating stacks of insulating and spacer material layers, and a metal-containing layer to induce metal-induced lateral crystallization, resulting in a cylindrical metal-semiconductor alloy region surrounding the vertical semiconductor channel, facilitating low resistance contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional contact formation methods are used for vertical semiconductor channels, then the manufacturing process is simpler, but the contact resistance is high
Solution Approach 1:
The patent applies preliminary action by depositing the metal-containing layer on the outer surface of the vertical semiconductor channel before final contact formation. This pre-positioned metal layer serves as a nucleation site for metal atom diffusion during annealing, enabling controlled crystallization and low-resistance contact formation without requiring complex post-processing steps
Solution Approach 2:
The patent utilizes parameter changes by performing a thermal anneal process that induces metal atom diffusion into the semiconductor channel. The annealing temperature and duration are controlled to achieve optimal metal atom migration, forming a metal-semiconductor alloy region that crystallizes the semiconductor material and creates a low-resistance contact path
2Reliability
If metal atoms diffuse into the vertical semiconductor channel to crystallize the channel, then the contact resistance decreases, but the manufacturing process complexity increases
Solution Approach 1:
The patent merges multiple functions into a single annealing step: metal atom diffusion, semiconductor channel crystallization, and contact resistance reduction all occur simultaneously during the same thermal processing step. This consolidation achieves multiple objectives without requiring separate process steps for each function
Solution Approach 2:
The metal-containing layer deposited on the outer surface of the vertical semiconductor channel acts as an intermediary. It provides a controlled source of metal atoms that diffuse into the channel during annealing, mediating the crystallization process and enabling low-resistance contact formation without direct contact between the contact structure and the channel
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of low resistance source-level contacts and crystallization of semiconductor channels, enhancing the efficiency and performance of three-dimensional memory devices by improving contact quality and reducing resistance.
Implementation Method 1
performing a first anneal process to induce a reaction of metal atoms in the metal-containing layer within a semiconductor material in the vertical semiconductor, wherein the metal atoms at least one of diffuse into the vertical semiconductor channel to crystallize the vertical semiconductor channel or form an alloy with a semiconductor material of the vertical semiconductor channel
Implementation Method 2
performing a first anneal process to induce a reaction of metal atoms in the metal-containing layer within a semiconductor material in the vertical semiconductor, wherein the metal atoms at least one of diffuse into the vertical semiconductor channel
Data Source
AI summary
A source-level sacrificial layer and an alternating stack of insulating layers and spacer material layers are formed over a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack and the source-level sacrificial layer, and memory opening fill structures are formed. A source cavity is formed by removing the source-level sacrificial layer, and exposing an outer sidewall of each vertical semiconductor channel in the memory opening fill structures. A metal-containing layer is deposited on physically exposed surfaces of the vertical semiconductor channel and the vertical semiconductor channel is crystallized using metal-induced lateral crystallization. Alternatively or additionally, cylindrical metal-semiconductor alloy regions can be formed around the vertical semiconductor channels to reduce contact resistance. A source contact layer can be formed in the source cavity.