Vertical Semiconductor Stack for Mixed Channel Integration
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Solution Overview
Problem
The integration of long channel and short channel semiconductor devices at the same device level is complex and leads to yield degradation and increased costs, while vertically stacking transistors poses challenges such as thermal impact from top transistors onto those at the bottom.
Innovation Solution
A vertically integrated semiconductor device is formed by separately creating short channel and long channel circuitries in different device layers, with short channel transistors fabricated in a silicon substrate and long channel transistors formed in a germanium layer or an oxide semiconductor layer above the silicon substrate, using low temperature processes to avoid impacting existing short channel circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If long channel and short channel devices are integrated at the same device level, then device functionality is achieved, but integration complexity increases and yield degrades
Solution Approach 1:
The patent transitions from planar integration to vertical stacking, moving devices from the same device level to different vertical layers. Short channel devices remain in the silicon substrate while long channel devices are formed in separately bonded semiconductor layers above, resolving the integration complexity issue while maintaining functionality.
Solution Approach 2:
The patent segments the integration process by separating long channel and short channel devices into distinct vertical layers. This segmentation allows each device type to be optimized independently with appropriate process conditions while achieving complete functionality through vertical integration.
2Device complexity
If transistors are vertically stacked, then integration complexity is reduced, but thermal impact from top transistors onto bottom transistors occurs
Solution Approach 1:
The patent introduces intermediate thermal management structures including thermal vias and thermal ground structures positioned between the short channel devices in the silicon substrate and long channel devices in the upper layers. These intermediaries conduct heat away from the upper devices, preventing thermal impact on the lower devices while enabling vertical integration.
3Object-affected harmful factors
If long channel devices are formed in separate layers using low temperature processes, then thermal impact on short channel circuitry is minimized, but process complexity increases
Solution Approach 1:
The patent performs preliminary actions by first forming the short channel devices in the silicon substrate, then bonding separate semiconductor layers containing long channel devices onto the substrate. This preliminary formation allows subsequent low temperature processing of the upper layers without affecting the already-formed short channel devices, minimizing thermal impact while managing process complexity through staged fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the integration process, reduces complexity, and improves yield by separating the formation of short channel and long channel transistors into different layers, while minimizing thermal impact and maintaining device performance.
Implementation Method 1
the Ge layer is formed directly on top of the first set of BEOL layers through a low temperature wafer bonding process
Implementation Method 2
the oxide semiconductor layer is formed directly on top of the second set of BEOL layers through a low temperature physical vapor deposition (LTPVD) process
Implementation Method 3
through a low temperature chemical vapor deposition (LTCVD) process
Data Source
AI summary
Embodiments of present invention provide a semiconductor device. The semiconductor device includes a silicon (Si) substrate containing a set of short channel field-effect-transistors (FETs); a germanium (Ge) layer on top of the Si substrate containing a set of long channel p-type FETs (PFETs); and an oxide semiconductor layer on top of the Ge layer containing a set of long channel n-type FETs (NFETs), wherein the set of short channel FETs, long channel PFETs, and long channel NFETs are interconnected through a set of far-back-end-of-line (FBEOL) layers.