Vertical Semiconductor Channel Structure for Reliable Substrate Contact
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Solution Overview
Problem
Vertical semiconductor devices face challenges in achieving uniform channel resistance and ensuring electrical connectivity between the channel structure and the substrate, leading to potential disconnections and increased resistance.
Innovation Solution
A method of manufacturing vertical semiconductor devices involves alternately forming insulation and sacrificial layers on a substrate, etching to form holes, and sequentially depositing semiconductor patterns and channel structures, with silicon ions implanted to form conductive patterns that directly contact the substrate, ensuring a stable channel structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional vertical memory device structures are used, then device complexity is reduced, but channel resistance uniformity deteriorates and electrical connectivity reliability worsens
Solution Approach 1:
The channel structure is divided into multiple segments including a first channel pattern on the sidewall and a second channel pattern on the substrate, with a blocking pattern separating them. This segmentation allows each part to be optimized independently for electrical connectivity while maintaining overall structural integrity.
Solution Approach 2:
The channel structure transitions from a traditional single-dimensional vertical arrangement to a two-dimensional configuration with patterns on both the sidewall and substrate surfaces. This dimensional change enables improved electrical connectivity through multiple contact points while managing structural complexity.
2Manufacturing precision
If the channel structure is simplified, then device complexity is reduced, but channel resistance uniformity deteriorates
Solution Approach 1:
Different regions of the channel structure are assigned different properties: the first channel pattern on the sidewall provides one set of electrical characteristics, while the second channel pattern on the substrate provides another. The blocking pattern creates localized regions with specific resistance characteristics, achieving overall uniformity through local optimization.
Solution Approach 2:
The blocking pattern is formed in advance between the first and second channel patterns to pre-establish the electrical connection path. This preliminary action ensures that subsequent channel patterns will achieve uniform resistance characteristics by following the pre-defined connection architecture.
3Reliability
If traditional channel structures are used, then device complexity is low, but disconnection risk increases
Solution Approach 1:
The blocking pattern serves as an intermediary element between the first channel pattern on the sidewall and the second channel pattern on the substrate. This mediator ensures reliable electrical connectivity by providing a defined interface and connection path, reducing disconnection risk while maintaining manufacturability through standard patterning processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved electrical characteristics by maintaining continuous contact between the channel structure and the substrate, reducing resistance and preventing disconnections, thereby enhancing device performance.
Implementation Method 1
when the second semiconductor pattern is formed, silicon ions may be implanted onto the second channel pattern in a direction substantially perpendicular to an upper surface of the substrate
Data Source
AI summary
In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.