Vertical Semiconductor Chip Stack with Partial Mold for Heat Dissipation
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Solution Overview
Problem
Existing semiconductor devices face challenges in efficiently integrating and cooling power semiconductor chips, particularly in vertical structures, where heat dissipation and electrical connectivity across multiple surfaces are complex and often inefficient.
Innovation Solution
The integration of semiconductor chips with vertical structures, where electrodes on opposite surfaces facilitate current flow, combined with a substrate and electrically conductive elements like metal clips or bond wires for connectivity, and a mold material for partial coverage, allowing for external heat sink attachment for effective heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power semiconductor chips are integrated into semiconductor devices with vertical structures, then electrical connectivity and heat dissipation are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The device is divided into multiple semiconductor chips (first, second, third chips) with distinct functions arranged in a vertical stack. Each chip handles specific electrical connections, allowing complex power electronics functions to be distributed across modular components rather than requiring a single complex chip design.
Solution Approach 2:
The patent transitions from planar chip arrangements to a vertical three-dimensional stacked configuration. Multiple chips are arranged vertically with electrodes on opposite surfaces facilitating current flow through the stack, enabling improved electrical connectivity and heat dissipation in the vertical dimension while compacting the horizontal footprint.
2Temperature
If multiple semiconductor chips are integrated vertically, then heat dissipation efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
Multiple semiconductor chips are merged into a single integrated device structure through vertical stacking and bonding. The chips are combined with a substrate and encapsulating material to form a unified power electronic device, enabling efficient heat dissipation through the integrated thermal pathways while maintaining compact form factor.
Solution Approach 2:
A substrate serves as an intermediary element between the stacked semiconductor chips, providing mechanical support, electrical connections, and thermal management. The substrate facilitates the integration of multiple chips while managing the manufacturing precision requirements by serving as a stable platform for chip mounting and interconnection.
3Power
If electrodes on opposite surfaces are used for current flow, then power handling capability is improved, but structural complexity increases
Solution Approach 1:
The patent utilizes vertical current flow paths through electrodes on opposite surfaces of stacked chips, transitioning from planar to three-dimensional current distribution. This vertical arrangement enables high power handling capability by distributing current through multiple chips in series while maintaining a compact horizontal footprint.
Solution Approach 2:
The power handling function is segmented across multiple semiconductor chips arranged vertically. Each chip contributes to the overall power capability, allowing the device to handle high power through distributed current paths rather than requiring a single large-power chip with complex internal structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables efficient electrical connectivity and heat dissipation in semiconductor devices, improving the performance and reliability of power semiconductor chips by allowing for better thermal management and structural integrity.
Implementation Method 1
An electrically conductive element may be involved, the electrically conductive element being electrically coupled to the second electrode of the second semiconductor chip and to the substrate
Implementation Method 2
allowing for external heat sink attachment for effective heat dissipation
Data Source
AI summary
A device with a plurality of semiconductor chips is disclosed. One embodiment provides a substrate. A first semiconductor chip is mounted over the substrate. A second semiconductor chip is mounted over the first semiconductor chip. A first electrically conducting element electrically couples the second semiconductor chip to the substrate and a mold material covers the first electrically conducting element only partially.