Vertical Semiconductor Chip Stacking with Conductive Bumps
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Solution Overview
Problem
Semiconductor packages face challenges in reducing size, improving performance, and enhancing reliability while maintaining low manufacturing costs, as existing methods struggle to efficiently connect semiconductor chips to terminals and protect them from the environment.
Innovation Solution
The method involves manufacturing semiconductor devices with a vertical structure, using a carrier with conductive bumps to bond semiconductor chips, and applying an encapsulant to protect the chips, allowing for efficient electrical connection and heat dissipation through a combination of bonding layers and bump structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional packaging methods are used, then manufacturing process is simple, but device size cannot be reduced and performance is limited
Solution Approach 1:
The patent transitions from planar/2D packaging to vertical/3D packaging by stacking multiple semiconductor chips vertically and connecting them through conductive bumps. This dimensional change enables significant reduction in device footprint while maintaining or enhancing functionality, directly resolving the contradiction between size reduction and structural complexity.
Solution Approach 2:
The patent implements a nested structure where multiple semiconductor chips are stacked vertically within a compact封装体, with each chip nested above the previous one. The conductive bumps penetrate through intermediate chips to establish electrical connections across multiple layers, creating a space-efficient nested arrangement that reduces overall device volume.
2Reliability
If chip connections are made through conventional methods, then manufacturing is easier, but electrical connectivity and heat dissipation are insufficient
Solution Approach 1:
The patent segments the electrical connection function into multiple conductive bumps distributed across the chip surfaces. Each bump acts as an independent connection point, and collectively they provide robust electrical connectivity and thermal management. This segmentation approach enhances reliability while maintaining manufacturing feasibility through standardized bump formation processes.
Solution Approach 2:
The conductive bumps serve dual functions: establishing electrical connections between chips and dissipating heat from the semiconductor devices. This multi-functionality resolves the contradiction by simultaneously improving electrical connectivity and thermal management without requiring separate dedicated structures, thereby maintaining ease of manufacture.
3Reliability
If protective encapsulation is added, then chip protection is improved, but manufacturing cost increases
Solution Approach 1:
The patent merges the protective encapsulation function with the existing packaging structure by forming a unified encapsulant that protects the stacked chips and integrates with the conductive bump connections. This consolidation provides comprehensive protection without requiring additional separate protective components, thereby controlling manufacturing costs while improving chip protection and overall device reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in high-performance, reliable semiconductor devices with reduced size and cost, enabling effective electrical and thermal management by using conductive bumps and encapsulants to enhance connectivity and protect the chips.
Implementation Method 1
at least two bumps made of a conductive material... efficient electrical connection... by using conductive bumps and encapsulants to enhance connectivity
Implementation Method 2
heat dissipation through a combination of bonding layers and bump structures... enabling effective electrical and thermal management
Data Source
AI summary
A method of manufacturing a semiconductor device includes providing a carrier and attaching a plurality of semiconductor chips to the carrier. The semiconductor chips have a first electrode pad on a first main face and at least a second electrode pad on a second main face opposite to the first main face, whereby the first electrode pad is electrically connected to the carrier. A plurality of first bumps are formed on the carrier, the first bumps being made of a conductive material. The carrier is then singulated into a plurality of semiconductor devices, wherein each semiconductor device includes at least one semiconductor chip and one first bump.