Vertical Semiconductor Chip Stacking for Miniaturization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices face challenges in miniaturization due to the need for electrical isolation between high-voltage and low-voltage semiconductor elements, which complicates the integration of inductors for power and microcomputer applications without damaging the microcomputer semiconductor element.
Innovation Solution
A semiconductor device configuration featuring a first semiconductor chip with a first inductor and a second semiconductor chip with a second inductor, where the inductors are electrically isolated and aligned to prevent voltage damage, allowing for miniaturization by optimizing the layout and bonding structure to facilitate efficient signal transmission and reduce interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the first semiconductor chip and second semiconductor chip are arranged with non-overlapping parts for wire bonding connection, then wire bonding can be performed, but the device area increases
Solution Approach 1:
The patent transitions from planar side-by-side arrangement to three-dimensional vertical stacking, where the second semiconductor chip is positioned above the first semiconductor chip through adhesive layers. This dimensional change allows both chips to occupy overlapping footprints while maintaining electrical isolation and enabling wire bonding through vertical vias and through-holes, thereby reducing the overall device area.
Solution Approach 2:
The patent implements a nested structure where the second semiconductor chip is effectively placed within the vertical projection area of the first semiconductor chip. The adhesive layers and through-holes create a nested arrangement that allows compact integration while maintaining access to bonding pads through via structures, resolving the contradiction between compact area and manufacturing accessibility.
2Reliability
If high-voltage and low-voltage semiconductor elements are electrically connected, then signal transmission is enabled, but the low-voltage element may be damaged
Solution Approach 1:
The patent introduces adhesive layers as intermediary structures between the high-voltage first semiconductor chip and the low-voltage second semiconductor chip. These adhesive layers provide electrical isolation while allowing mechanical bonding and signal transmission through controlled vias, acting as a mediator that enables communication while protecting against voltage damage.
Solution Approach 2:
The patent segments the electrical connection path into isolated sections using adhesive layers and through-holes. The bonding pads are electrically isolated on each chip, with signal transmission achieved through controlled conductive paths in the adhesive layers, creating segmented electrical zones that prevent direct high-voltage exposure to low-voltage elements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables miniaturization of semiconductor devices while maintaining high communication accuracy and preventing voltage-related damage, simplifying the assembly process and enhancing the device's characteristics.
Implementation Method 1
This makes it possible to transmit signals to each other between the semiconductor element for electric power and the semiconductor element for the MCU by electromagnetic induction coupling via the first inductor and the second inductor.
Data Source
AI summary
A semiconductor device includes a first semiconductor chip, an adhesive layer that is formed on the first semiconductor chip, and a second semiconductor chip that is arranged on the first semiconductor chip via the adhesive layer. The first semiconductor chip has a first semiconductor substrate and a first wiring layer. The first wiring layer has a first inductor and a first electrode pad. The first wiring layer is formed on the first semiconductor substrate. The second semiconductor chip has a second wiring layer and a second semiconductor substrate. The second wiring layer is formed on the first wiring layer via the adhesive layer. The second semiconductor substrate is formed on the second wiring layer, and has a first opening. In a plan view, the first electrode pad is formed so as not to overlap with the second semiconductor chip, and a second electrode pad overlaps with the first opening.