Vertical Semiconductor Structure With Curved Sidewalls for Dense Integration
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high reliability, high speed, and multifunctionality while maintaining complex structures and high integration density, which are essential for meeting increasing demands in the electronic industry.
Innovation Solution
A semiconductor device design featuring active patterns with long and short sidewalls, epitaxial patterns, and gate electrodes that surround the active patterns, enhancing electrical characteristics and integration density through a selective epitaxial growth process and advanced layout configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional planar transistor structures are used, then manufacturing process is simple, but integration density and electrical characteristics are limited
Solution Approach 1:
The patent transitions from conventional planar (2D) transistor structures to vertical (3D) transistor structures by forming active patterns that extend vertically from the substrate. This dimensional change increases the effective channel area and integration density without proportionally increasing the footprint area, thereby resolving the contradiction between integration density and structure complexity.
Solution Approach 2:
The patent implements nested structures where lower epitaxial patterns are formed within recesses of the substrate, active patterns are formed on top of lower epitaxial patterns, and upper epitaxial patterns are formed on top of active patterns. This nesting approach maximizes vertical space utilization and increases integration density while maintaining a compact overall structure.
2Manufacturing precision
If vertical field effect transistor structures are implemented, then integration density improves, but manufacturing process complexity increases
Solution Approach 1:
The patent divides the vertical transistor structure into distinct segments: lower epitaxial patterns, active patterns, and upper epitaxial patterns. Each segment is formed through separate epitaxial growth processes, allowing independent optimization and control of each layer's properties. This segmentation simplifies the manufacturing process by breaking down the complex vertical structure formation into manageable sequential steps.
Solution Approach 2:
The patent performs preliminary actions by forming lower epitaxial patterns first, then using them as foundations for subsequent active pattern formation. The lower epitaxial patterns are grown in recesses before the active patterns are formed on top, preparing the structure in advance for the next fabrication steps and enabling better control over the final vertical transistor characteristics.
3Reliability
If curved sidewalls are formed in active patterns, then electrical characteristics improve, but manufacturing precision requirements increase
Solution Approach 1:
The patent intentionally forms curved sidewalls in the active patterns instead of straight vertical sidewalls. This curvature is achieved through controlled epitaxial growth processes that allow the sidewalls to naturally curve during formation. The curved geometry improves electrical characteristics by optimizing the electric field distribution in the channel region, while the curvature is controlled through process parameters rather than requiring ultra-precise post-forming adjustments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design improves electrical characteristics and integration density, enabling the semiconductor device to meet the demands for high reliability and multifunctionality, supporting complex structures and high integration while maintaining efficient performance.
Implementation Method 1
a lower epitaxial pattern on the substrate and covering a part of the active pattern, a gate electrode on the lower epitaxial pattern and extending along the long sidewalls of the active pattern, and an upper epitaxial pattern on the active pattern and connected to an upper surface of the active pattern
Data Source
AI summary
There is provided a semiconductor device capable of improving electrical characteristics and integration density. The semiconductor device includes an active pattern protruding from a substrate, the active pattern including long sidewalls extending in a first direction and opposite to each other in a second direction, a lower epitaxial pattern on the substrate and covering a part of the active pattern, a gate electrode on the lower epitaxial pattern and extending along the long sidewalls of the active pattern, and an upper epitaxial pattern on the active pattern and connected to an upper surface of the active pattern. The active pattern includes short sidewalls connecting with the long sidewalls of the active pattern, and at least one of the short sidewalls of the active pattern has a curved surface.