Vertical Semiconductor Device With Gate Electrodes Between Mesas
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Solution Overview
Problem
Existing semiconductor devices, such as planar DMOSFETs, require large chip areas for low on-state resistance and high voltage applications, leading to increased costs, while trench-MOSFETs offer reduced area but complex manufacturing and limited benefits in energy-limited products due to additional chip area requirements for energy dissipation and signal pads.
Innovation Solution
A method for producing vertical semiconductor devices involves forming deep trenches and semiconductor mesas on a wafer with pre-formed pn-junctions, using a stacked hard mask layer to etch trenches and create gate electrodes, and forming shallow trenches for conductive regions, resulting in a semiconductor body with gate electrodes between mesas and backside metallization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If planar DMOSFETs are used to achieve low on-state resistance at high voltage, then the device performance is improved, but the chip area required increases leading to higher costs
Solution Approach 1:
The patent transitions from planar (2D) gate electrode structures to vertical (3D) gate electrode structures that extend into trenches. This dimensional change allows the gate to control current flow more efficiently in the vertical direction, achieving low on-state resistance with reduced chip area by utilizing the third dimension for current conduction paths.
Solution Approach 2:
The patent divides the semiconductor substrate into multiple cell units with individual trenches and gate electrodes. Each cell is segmented with isolated trenches containing gate electrodes, allowing parallel current paths through multiple cells. This segmentation enables scaling of current capacity without proportionally increasing chip area, as cells can be tightly packed in a grid pattern.
2Area of stationary object
If trench-MOSFETs are used to reduce chip area, then the chip area is reduced, but the manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary doping of the semiconductor substrate to form pn-junctions and define cell regions before trench formation. The semiconductor layers with different conductivity types are pre-established in the substrate, so that when trenches are later etched and filled with gate electrodes, the doping structure is already in place. This preliminary action simplifies subsequent manufacturing steps compared to forming trenches first and then attempting to dope through complex processes.
3Area of stationary object
If trench-MOSFETs are used to reduce chip area, then the chip area is reduced, but additional chip area is still required for energy dissipation and signal pads limiting benefits in energy-limited products
Solution Approach 1:
The patent designs the semiconductor substrate with pn-junctions and doped regions that serve multiple functions: they form the active switching cells, provide current conduction paths, and enable energy dissipation through the vertical junction structures. The same semiconductor layers that create the low on-state resistance channels also provide the drift regions necessary for voltage blocking and energy dissipation, eliminating the need for separate dedicated areas for these functions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces chip area requirements while simplifying manufacturing and reducing costs by forming vertical semiconductor devices with efficient energy dissipation and signal pad placement, addressing the limitations of both planar and trench-MOSFETs.
Implementation Method 1
etching the hard mask to form second openings in the hard mask at the main surface of the semiconductor mesas
Data Source
AI summary
A vertical semiconductor device includes a semiconductor body having a backside and extending, in a peripheral area and in a vertical direction substantially perpendicular to the backside, from the backside to a first surface of the semiconductor body, the body including in an active area spaced apart semiconductor mesas extending, in the vertical direction, from the first surface to a main surface arranged above the first surface, in a vertical cross-section the peripheral area extending between the active area and an edge that extends between the back-side and the first surface, in the vertical cross-section each of the mesas including first and second side walls, a first pn-junction extending between the first and second side walls, and a conductive region in Ohmic contact with the mesa and extending from the main surface into the mesa. Gate electrodes are arranged between adjacent mesas and extend across the first pn-junctions.