Vertical Semiconductor Device Pillar Structure Integration
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Solution Overview
Problem
Existing vertical structure transistors face limitations in integration and current drivability due to the step between cell and peripheral areas, and require alternative solutions to improve voltage drop and reduce source resistance.
Innovation Solution
A vertical type semiconductor device is fabricated with a common source region, channel region, and drain region formed on a semiconductor substrate, where the channel region has a specific height and diameter, and a first gate electrode surrounds the channel region, allowing for reduced external resistance and improved current drivability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a vertical structure transistor is formed by etching the semiconductor substrate in the cell area, then current drivability is improved, but a step is created between the cell area and peripheral area that prevents desired integration
Solution Approach 1:
The patent transitions from horizontal transistor structures to vertical transistor structures by forming pillars extending in the vertical dimension. This dimensional change allows current to flow vertically through the channel rather than horizontally, improving current drivability while enabling better integration density as multiple devices can be stacked vertically
Solution Approach 2:
The patent applies different structures to different areas: vertical transistors are formed in the cell area while horizontal transistors are formed in the peripheral area. This local differentiation allows each area to have the structure best suited for its function, with the cell area benefiting from the superior current drivability of vertical structures
2Ease of manufacture
If transistors are formed in a horizontal structure, then manufacturing is simpler, but the reduction rate of operation voltage is restricted
Solution Approach 1:
The patent forms transistors with channels extending in the vertical dimension rather than horizontally. This vertical channel structure reduces the channel length more effectively, enabling lower operation voltages while maintaining manufacturability through established vertical fabrication processes
3Device complexity
If diodes are formed on a word line, then device complexity is reduced, but resistance of the word line varies according to locations causing word line bounce
Solution Approach 1:
The patent inverts the conventional approach by using vertical transistors instead of diodes as the access device. This inversion allows for better control of the access device characteristics, enabling lower threshold voltages and reduced word line resistance variations, thereby eliminating word line bounce while maintaining structural simplicity
Data Source
AI summary
A vertical memory device and a method of fabricating the same are provided. The vertical type semiconductor device includes a common source region formed in a cell area of a semiconductor substrate. A channel region is formed on the common source region. The channel region has a predetermined height and a first diameter. A drain region is formed on the channel region. The drain region has a predetermined height and a second diameter larger than the first diameter. A first gate electrode surrounding the channel region.