Vertical Semiconductor Device Substrate Recess Prevention
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Solution Overview
Problem
Conventional memory devices with vertical transistors experience a reduction in cell current due to recesses formed in the substrate, which affects the manufacturing process and device performance.
Innovation Solution
A vertical semiconductor device design featuring a channel structure with a protruding region on its side wall, a gate insulating layer extending along the channel structure, and etch stop layers to prevent recess formation on the substrate, enhancing electrical characteristics by reducing contact resistance and maintaining a flat substrate surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If recesses are formed in the substrate when forming a channel hole in conventional vertical transistor memory devices, then the channel hole can be formed to enable vertical transistor structure, but this causes an undesirable reduction of cell current in the memory device
Solution Approach 1:
A flat layer is formed on the substrate before forming the channel hole, and this flat layer extends into the channel hole to maintain a flat bottom surface. This preliminary action prevents the formation of recesses in the substrate that would otherwise occur during channel hole etching, thereby maintaining cell current while enabling vertical transistor structure.
Solution Approach 2:
The flat layer acts as an intermediary material between the substrate and the channel hole structure. It provides a flat surface that prevents direct contact between the etching process and the substrate, thereby preventing recess formation while still allowing the channel hole to be formed for vertical transistor operation.
2Shape
If recesses are formed in the substrate during vertical transistor manufacturing, then the vertical structure can be achieved, but the manufacturing process becomes more complex and cell current is reduced
Solution Approach 1:
The flat layer is deposited on the substrate before channel hole formation, creating a preliminary flat surface that simplifies subsequent manufacturing steps. This prevents the need for additional recess-filling processes that would otherwise be required, thereby reducing manufacturing complexity while maintaining the vertical transistor structure.
3Reliability
If the substrate surface is kept flat without recesses, then cell current is maintained, but it becomes difficult to form the vertical channel structure
Solution Approach 1:
The flat layer is formed on the substrate before channel hole etching, and it extends into the channel hole to maintain a flat bottom surface. This preliminary structure enables vertical channel formation while preventing substrate recesses, thereby maintaining cell current.
Solution Approach 2:
The flat layer extends in the vertical dimension into the channel hole, providing support and maintaining flatness at the bottom surface. This dimensional extension allows the vertical channel structure to be formed without creating recesses in the substrate, thereby maintaining cell current.
Data Source
AI summary
A vertical semiconductor device includes a channel structure extending from a substrate in a first direction perpendicular to an upper surface of the substrate, and a ground selection line, word lines, and a string selection line sequentially formed on a side surface of the channel structure in the first direction to be separated from one another. The channel structure includes a protruding region formed in a side wall portion of the channel structure between the ground selection line and the upper surface of the substrate, the protruding region protruding in a horizontal direction perpendicular to the first direction.