Vertical Semiconductor Device Trench Isolation
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Solution Overview
Problem
The challenge lies in increasing the density of transistors on semiconductor substrates without further reducing the minimum feature size, as traditional planar MOS transistors face limitations in manufacturing cost and yield due to the difficulty in isolating and making electrical contacts with vertical transistors.
Innovation Solution
A vertical semiconductor device is fabricated with a trench in the substrate, featuring a channel along the trench wall, a drain region at the top, a source region at the bottom, and a gate electrode overlying the channel, allowing for increased transistor density without shrinking feature sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical transistors are fabricated in trenches to increase transistor density, then the number of devices that can be integrated increases, but the difficulty of isolating transistors and making electrical contacts increases
Solution Approach 1:
The patent transitions from planar transistors to vertical transistors by utilizing the third dimension (depth) of the substrate. Trenches are etched into the substrate to create vertical channels, allowing current flow in the vertical direction rather than lateral flow. This dimensional change enables higher device density while maintaining manufacturability through established trench fabrication techniques.
Solution Approach 2:
The patent segments the substrate into multiple isolated trenches, each containing a vertical transistor. The trenches are separated by isolation regions, effectively dividing the substrate into independent device units. This segmentation approach solves the isolation problem by physically separating adjacent transistors while maintaining individual electrical contact access to each device.
2Quantity of substance
If the minimum feature size is reduced to pack more transistors, then transistor density increases, but manufacturing cost increases and yield decreases
Solution Approach 1:
Instead of reducing the lateral minimum feature size, the patent increases transistor density by extending transistors vertically into the substrate. The channel length is oriented in the vertical direction along the trench walls, allowing more transistors to be packed per unit surface area without reducing the lateral dimensions of individual devices, thereby avoiding the associated manufacturing challenges.
Solution Approach 2:
The patent embeds vertical transistor structures within trenches that are formed in the substrate. Multiple transistor components (channel, source, drain, gate) are nested within the trench structure, with the channel forming along the trench walls and the gate wrapping around the channel. This nesting approach maximizes space utilization without requiring smaller feature sizes.
3Quantity of substance
If vertical transistors are used to increase device integration, then the number of devices per IC increases, but the complexity of making necessary electrical contacts increases
Solution Approach 1:
The patent isolates each vertical transistor in its own trench, with each trench serving as an independent electrical unit. This segmentation allows for simplified contact schemes where each trench can be accessed independently through the substrate surface, reducing the complexity of routing and contacting multiple devices compared to densely packed planar structures.
Solution Approach 2:
By orienting the transistor channel vertically, the patent enables electrical contacts to be made at the substrate surface level for source and drain regions, rather than requiring contacts through the substrate thickness. The gate is formed as an overlaying structure that can be accessed from the surface, simplifying the overall contact architecture despite the vertical device orientation.
Data Source
AI summary
A semiconductor device and methods for its fabrication are provided. The semiconductor device comprises a trench formed in the semiconductor substrate and bounded by a trench wall extending from the semiconductor surface to a trench bottom. A drain region and a source region, spaced apart along the length of the trench, are formed along the trench wall, each extending from the surface toward the bottom. A channel region is formed in the substrate along the trench wall between the drain region and the source region and extending along the length of the trench parallel to the substrate surface. A gate insulator and a gate electrode are formed overlying the channel.