Vertical Semiconductor Dummy Structures for Etching Defect Control
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Solution Overview
Problem
In vertical semiconductor devices, the arrangement and density of memory cells are limited by defects in dummy structures, leading to electrical failures and reduced operational efficiency due to variations in dummy hole widths and spacings, particularly in the second dummy region where not open failures and etching loading issues occur.
Innovation Solution
The design includes a substrate with distinct regions, featuring conductive patterns and dummy structures with varying widths and spacings, where the second dummy structures have wider upper surfaces and increased spacings, reducing defects and improving contact between layers by optimizing the arrangement and shape of dummy structures in the second dummy region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy structures are formed with uniform width and spacing, then manufacturing process is simple, but defects occur due to etching loading variations and not open failures
Solution Approach 1:
The patent applies local quality by differentiating dummy structure characteristics based on their position. First dummy structures adjacent to the cell region have uniform width and spacing, while second dummy structures in the second dummy region have progressively wider upper surfaces and increased spacing. This local differentiation resolves the contradiction by optimizing each region's dummy structures for its specific functional requirements, improving overall reliability without excessive complexity.
Solution Approach 2:
The patent changes geometric parameters of dummy structures to resolve the contradiction. Specifically, the upper surface width of second dummy structures is progressively increased, and spacing between them is enlarged compared to first dummy structures. These parameter changes reduce etching loading variations and prevent not open failures, thereby improving reliability while maintaining manageable device complexity.
2Reliability
If second dummy structures have larger spacing, then not open failures are reduced, but arrangement density decreases
Solution Approach 1:
The patent applies local quality by implementing different spacing strategies in different regions. First dummy structures have smaller spacing to maintain density, while second dummy structures have larger spacing to prevent not open failures. This regional differentiation allows the patent to improve contact reliability in the second dummy region without significantly compromising overall arrangement density.
Solution Approach 2:
The patent resolves the contradiction by utilizing the vertical dimension through tapered structures. The second dummy structures have wider upper surfaces, which provides improved contact area and reliability in the horizontal plane without requiring increased horizontal spacing. This dimensional approach allows larger effective contact area while maintaining compact arrangement.
Data Source
AI summary
A vertical semiconductor device includes a substrate with a first and second region. A conductive pattern on the first region extends in a first direction. The first region includes a cell region, a first dummy region and a second dummy region. The conductive pattern extends in a first direction. A pad is disposed on the second region, the pad contacts a side of the conductive pattern. A plurality of first dummy structures extends through the conductive pattern on the first dummy region. A plurality of second dummy structures extend through the conductive pattern on the second dummy region, the second dummy structures disposed in a plurality of columns that extend in a second direction perpendicular to the first direction. Widths of upper surfaces of the second dummy structures are different in each column, and the widths of upper surfaces of the second dummy structures increase toward the second region.