Vertical Semiconductor Device Dummy Wordline Planarization
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Solution Overview
Problem
The challenge in semiconductor devices is to achieve high integration density while minimizing costs, as traditional two-dimensional memory devices face limitations in pattern formation and integration due to the need for expensive equipment, whereas three-dimensional devices with vertical semiconductor pillars offer increased integration but require complex planarization and interconnection processes.
Innovation Solution
A vertical-type semiconductor device with a dummy wordline structure and a dampproofing structure within the dummy wordline structure is introduced, facilitating planarization and minimizing moisture and contamination, which includes a semiconductor substrate with vertically stacked wordlines, a gate dielectric, and a dummy wordline structure of equal height in the peripheral circuit region, along with a dampproofing structure, such as a silicon nitride layer, to protect against external contaminants.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory cells with vertical semiconductor pillars are used, then integration density is significantly increased, but planarization process complexity increases
Solution Approach 1:
The patent creates a dummy wordline structure that copies the vertical pillar structure of the actual wordline but is positioned in the peripheral circuit region where it serves as a planarization aid rather than a functional element. This dummy structure allows the interlayer dielectric to be planarized uniformly without requiring complex multi-step processes.
Solution Approach 2:
The dummy wordline structure is selectively placed only in the peripheral circuit region, not in the cell array region. This local application provides planarization benefits where needed (peripheral circuits) while maintaining the compact vertical structure where high density is critical (cell array).
2Ease of manufacture
If dummy wordline structure is added for planarization, then manufacturing cost is reduced, but device structure complexity increases
Solution Approach 1:
The dummy wordline structure serves multiple functions: it acts as a planarization reference for the interlayer dielectric, provides a structural template for alignment, and creates a uniform surface for subsequent peripheral circuit fabrication. This multi-functionality justifies the additional structure by eliminating the need for separate planarization processes.
Solution Approach 2:
The dummy wordline structure is formed during the same fabrication steps as the actual wordline, before the interlayer dielectric deposition. This preliminary action ensures that the planarization reference is already in place when the dielectric is applied, simplifying the overall manufacturing sequence.
3Adaptability or versatility
If peripheral circuit region is separated from cell region, then device functionality is improved, but moisture and contamination resistance is reduced
Solution Approach 1:
The dummy wordline structure is nested within the peripheral circuit region, creating a contained structure that physically blocks moisture and contaminants from reaching the interface between the cell array and peripheral circuits. The dummy structure acts as a protective barrier while maintaining the functional separation needed for device operation.
Data Source
AI summary
A vertical-type semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region, a wordline structure on the cell region of the semiconductor substrate, the wordline structure including a plurality of wordlines stacked on top of each other, a semiconductor structure through the wordline structure, a gate dielectric between the wordline structure and the semiconductor structure, and a dummy wordline structure on the peripheral circuit region, the dummy wordline structure having a vertical structure and including same components as the wordline structure.