Vertical Semiconductor Structure for Footprint Scaling and Gate Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing planar semiconductor devices face challenges in scaling down their footprint due to the parallel arrangement of source, gate, and drain, which leads to increased power consumption and resistance.
Innovation Solution
A vertical semiconductor device is designed with a substrate, where first and second source/drain layers, a channel layer, and a gate stack are stacked in sequence, allowing for a reduced footprint and improved control over gate length through epitaxial growth of the channel layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar device architecture is used with parallel arrangement of source, gate and drain, then device structure is simple to manufacture, but footprint area cannot be scaled down further leading to increased power consumption and resistance
Solution Approach 1:
The patent transitions from a planar two-dimensional arrangement to a vertical three-dimensional stacked architecture. The source, gate, and drain are arranged vertically with the gate stack positioned between the first and second source/drain layers, enabling the device to utilize the third dimension (vertical direction) for component placement. This dimensional change allows significant reduction in footprint area while maintaining manufacturability through established epitaxial growth and stacking processes.
2Ease of manufacture
If planar device architecture is used, then manufacturing process is straightforward, but device performance deteriorates due to increased power consumption and resistance
Solution Approach 1:
By stacking the source, gate, and drain vertically, the patent achieves shorter current paths and reduced resistance while maintaining a straightforward manufacturing process based on sequential epitaxial growth. The vertical arrangement allows the gate to effectively control the channel between source and drain regions without requiring lateral scaling, thus improving device performance without complicating the manufacturing approach.
Solution Approach 2:
The gate stack is nested between the first and second source/drain layers in a vertically stacked configuration. This nesting arrangement allows the gate to be positioned precisely where it can control the channel current, improving device performance through better electrostatic control while maintaining a compact structure that is compatible with standard semiconductor manufacturing processes.
3Area of moving object
If vertical device architecture is used with stacked source/drain layers and gate stack, then footprint area is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent employs vertical stacking to reduce footprint area, arranging the first source/drain layer, channel layer, and second source/drain layer in the vertical direction with the gate stack positioned between them. This three-dimensional configuration compresses the device structure vertically, achieving compact footprint while the regular stacked architecture actually simplifies the manufacturing process compared to complex lateral arrangements.
4Ease of manufacture
If gate length is controlled by lithography in planar devices, then manufacturing is easier, but gate length control precision is insufficient for scaling
Solution Approach 1:
The patent replaces lithography-based gate length definition with epitaxial growth-based control. The gate length is determined by the thickness of the channel layer, which is precisely controlled during the epitaxial growth process. This substitution of the mechanical lithography process with a controlled chemical epitaxial process enables superior gate length precision and better scalability while maintaining manufacturing feasibility.
Solution Approach 2:
The patent changes the controlling parameter for gate length from lateral dimensions (controlled by lithography) to vertical thickness (controlled by epitaxial growth). By defining gate length through the channel layer thickness rather than lateral patterning, the device achieves precise gate length control that is essential for further scaling, while the epitaxial growth process remains a well-established manufacturing technique.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The vertical device architecture enables efficient scaling down of the device footprint, reduces parasitic capacitance, and enhances carrier mobility and current handling capabilities due to the use of single-crystalline semiconductor materials.
Implementation Method 1
forming channel layers on the first source/drain layer which are substantially co-planar in a first device region and a second device region
Data Source
AI summary
There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate, and a first device and a second device formed on the substrate. Each of the first device and the second device includes a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and also a gate stack surrounding a periphery of the channel layer. The channel layer of the first device and the channel layer of the second device are substantially co-planar.