Vertical Semiconductor Device Gate Pattern Segmentation
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Solution Overview
Problem
Vertical semiconductor devices with vertically stacked memory cells often experience poor electrical characteristics due to leakage current and reliability issues, particularly in the design of gate and semiconductor pattern interactions.
Innovation Solution
The design includes a conductive pattern structure with a first gate pattern and vertically stacked second gate patterns on a substrate, where the second channel hole is positioned within an opening of the first gate pattern, preventing contact between the second semiconductor pattern and the first gate pattern, thus minimizing leakage current and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are vertically stacked to increase storage density, then device capacity increases, but electrical characteristics deteriorate due to leakage current
Solution Approach 1:
The gate pattern is segmented into a first gate pattern and second gate pattern, with the second gate pattern having openings that divide it into multiple regions. This segmentation prevents the semiconductor pattern from forming a continuous conductive path through the entire gate structure, thereby reducing leakage current while maintaining vertical stacking for high storage density
Solution Approach 2:
The second gate pattern is designed with different local properties: regions with openings (where semiconductor pattern is blocked) and regions without openings (where semiconductor pattern can contact). This local differentiation allows selective electrical isolation in specific areas to prevent leakage while maintaining functionality in other areas
2Ease of operation
If semiconductor pattern contacts gate pattern to ensure electrical connection, then device functionality is maintained, but leakage current increases
Solution Approach 1:
The openings in the second gate pattern act as intermediary structures that selectively block the semiconductor pattern from contacting the first gate pattern. This intermediary design allows electrical connection where needed while preventing harmful leakage current through strategic isolation zones
Data Source
AI summary
A vertical semiconductor device may include a first gate pattern, second gate patterns, a first channel hole, a first semiconductor pattern, a second channel hole, and a second semiconductor pattern. The first gate pattern may extend in a first direction on a substrate including first and second regions. The first direction may be parallel to an upper surface of the substrate, and a portion of the first gate pattern on the second region may include a first opening. The second gate patterns may be vertically stacked and spaced apart from each other on the first gate pattern, and each of the second gate patterns may extend in the first direction. The first channel hole may extend through the second gate patterns and the first gate pattern and expose a first portion of the substrate on the first region of the substrate. The first semiconductor pattern may be at a lower portion of the first channel hole. The second channel hole may extend through the second gate patterns and expose a second portion of the substrate on the second region of the substrate, and the second channel hole may be disposed within an area of the first opening in a plan view, wherein the first opening has a larger area than the second channel hole in a plan view. The second semiconductor pattern may be at a lower portion of the second channel hole.