Vertical Semiconductor Device with Surrounding Gate Stack
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Solution Overview
Problem
Conventional planar semiconductor devices face challenges in scaling down their footprint due to the parallel arrangement of source, gate, and drain, leading to increased power consumption and resistance, making it difficult to further reduce the device area.
Innovation Solution
A vertical semiconductor device is designed with a substrate, stacked source/drain layers, and a channel layer, where the gate stack surrounds the channel layer, allowing for controlled gate length and reduced parasitic capacitance, and utilizing epitaxial growth for precise layer formation and single-crystalline semiconductor materials for enhanced carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If planar device architecture is used with parallel arrangement of source, gate and drain, then device area can be reduced, but power consumption increases and resistance increases
Solution Approach 1:
The patent transitions from a planar two-dimensional arrangement to a vertical three-dimensional architecture. The source, gate and drain are stacked vertically with the gate surrounding the channel in the vertical direction, allowing current to flow vertically through the channel rather than laterally. This dimensional change enables reduced footprint area while maintaining lower resistance and power consumption paths.
2Area of stationary object
If planar device architecture is used with parallel arrangement of source, gate and drain, then device area can be reduced, but resistance increases
Solution Approach 1:
The vertical stacking architecture repositions the current conduction path from lateral to vertical direction. The channel extends vertically between the source and drain with the gate surrounding it, creating a more direct current path that reduces resistance compared to the lateral current flow in planar devices of equivalent footprint.
3Manufacturing precision
If gate stack surrounds the periphery of the channel layer, then gate length can be well controlled through epitaxial growth, but device structure becomes more complex
Solution Approach 1:
The patent positions the gate stack to surround the channel layer in the vertical direction, with the gate length determined by the channel layer thickness. This vertical arrangement allows precise control of gate length through epitaxial growth processes that excel at controlling thin film thickness, rather than relying on lateral lithographic patterning which has resolution limits.
Solution Approach 2:
The invention changes the critical dimension control parameter from lateral width (in planar devices) to vertical thickness (in vertical devices). By controlling the channel layer thickness through epitaxial growth, the gate length can be precisely controlled at dimensions that would be difficult to achieve with conventional lithography, thereby improving manufacturing precision despite increased structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The vertical device architecture enables effective scaling of the device footprint, improves carrier mobility, reduces current leakage, and enhances overall performance by controlling gate length and minimizing parasitic capacitance.
Implementation Method 1
The channel layer may be formed by, for example, epitaxy, and thus the thickness thereof can be well controlled
Data Source
AI summary
There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate, and a first device and a second device formed on the substrate. Each of the first device and the second device includes a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and also a gate stack surrounding a periphery of the channel layer. The channel layer of the first device and the channel layer of the second device are substantially co-planar.