Vertical Semiconductor Interconnects with Epitaxial Diodes
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Solution Overview
Problem
Existing methods for forming integrated circuit memory devices, particularly nonvolatile memory cells using phase-changeable materials, face challenges in achieving high integration and efficient formation of semiconductor diodes with precise control over etch stop layers and epitaxial growth, leading to suboptimal performance and reliability.
Innovation Solution
The method involves forming an etch stop layer on a semiconductor substrate, patterning an interlayer insulating layer to expose a portion of the etch stop layer, removing it using wet etching to create an undercut opening, and selectively growing semiconductor regions with epitaxial doping to form a P-N rectifying junction, with additional steps for cleaning and spacer layer deposition to enhance growth and device integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods are used to form semiconductor diodes in phase-changeable memory cells, then basic functionality is achieved, but integration density and manufacturing precision are suboptimal
Solution Approach 1:
An etch stop layer is formed on the semiconductor substrate before subsequent processing steps. This preliminary layer enables precise control over the etching depth when forming the semiconductor diode, ensuring that the diode is formed at the correct depth without affecting underlying structures. The etch stop layer acts as a predetermined barrier that stops the etching process at the desired location.
Solution Approach 2:
The etch stop layer serves as an intermediary element between the semiconductor substrate and the interlayer insulating layer. It mediates the etching process by providing a distinct stopping point, allowing selective removal of material above the etch stop layer while preserving the substrate and underlying structures. This intermediary layer simplifies the overall process control.
2Productivity
If vertical stacking is used to achieve high integration, then device density increases, but control over epitaxial growth and junction formation becomes more difficult
Solution Approach 1:
The semiconductor diode is formed as a vertically stacked structure with distinct segments: a first semiconductor region, a second semiconductor region, and a P-N rectifying junction between them. Each segment is formed through controlled epitaxial growth steps, allowing independent optimization of each region's properties while maintaining precise vertical alignment. The segmentation enables high integration density through vertical stacking while preserving manufacturing precision through controlled growth of each segment.
Solution Approach 2:
The invention transitions from planar diode formation to vertical stacking, utilizing the vertical dimension to achieve high integration density. By forming the semiconductor diode vertically through the thickness of the substrate, multiple functional regions can be stacked in the vertical direction, increasing device density without compromising the precision of each individual region's formation through controlled epitaxial growth.
3Ease of manufacture
If wet etching is used to remove etch stop layer, then selective removal is improved, but undercut formation may affect subsequent growth uniformity
Solution Approach 1:
The wet etching process selectively removes the etch stop layer with different etching rates for different materials. The etch stop layer is removed locally where exposed, creating an undercut structure that provides lateral support. This selective local removal facilitates easy manufacture by enabling simple wet etching chemistry to achieve precise depth control, while the resulting undercut geometry actually supports uniform subsequent epitaxial growth by providing a stable base.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of high-integration nonvolatile memory devices with improved semiconductor diodes, enhancing data storage capabilities and device reliability by ensuring precise control over the growth of semiconductor regions and the formation of rectifying junctions.
Implementation Method 1
This removal of the etch stop layer may be performed by wet etching the first portion of the etch stop layer using a phosphoric acid solution, for example.
Implementation Method 2
This cleaning solution may include hydrofluoric acid.
Implementation Method 3
A semiconductor region is then selectively grown into the vertical opening, using the exposed portion of the surface of the semiconductor substrate as an epitaxial seed.
Implementation Method 4
An annealing step may also be performed to thereby activate the first and second conductivity type dopants and define a P-N rectifying junction therein.
Data Source
AI summary
Methods of forming integrated circuit devices include forming an etch stop layer on a surface of a semiconductor substrate and forming a first interlayer insulating layer on the etch stop layer. The first interlayer insulating layer is patterned to define an opening therein that exposes a first portion of the etch stop layer. This first portion of the etch stop layer is then removed to thereby expose an underlying portion of the surface of the semiconductor substrate. This removal of the etch stop layer may be performed by wet etching the first portion of the etch stop layer using a phosphoric acid solution. A semiconductor region is then selectively grown into the opening, using the exposed portion of the surface of the semiconductor substrate as an epitaxial seed layer.