Vertical Semiconductor Isolation Sidewall for Lower Parasitic Capacitance
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Solution Overview
Problem
Conventional vertical semiconductor devices face performance limitations due to high parasitic capacitance, which hinders their ability to meet the growing demand for high-performance semiconductor devices.
Innovation Solution
A method for manufacturing semiconductor devices involves forming a first and second electrode layer, etching the semiconductor layer to create cavities and channel layers, filling these cavities with dummy gate layers, and then removing parts to form recesses that are filled with dielectric material to reduce parasitic capacitance, thereby improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional vertical semiconductor device structure is used, then device integration density is improved, but parasitic capacitance increases
Solution Approach 1:
The patent extracts the harmful parasitic capacitance by removing portions of the semiconductor layer to form cavities, and by removing portions of the gate layer to form recesses. This extraction of material reduces the parasitic capacitance between the gate electrode and source/drain electrodes while maintaining the vertical device structure for high integration density.
Solution Approach 2:
The patent applies local quality by creating cavities in specific regions of the semiconductor layer and recesses in specific regions of the gate layer. These localized structural modifications reduce parasitic capacitance in critical areas without affecting the overall vertical device architecture, thereby maintaining high integration density while improving electrical characteristics.
2Object-generated harmful factors
If semiconductor layer is etched to form cavity, then parasitic capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent segments the manufacturing process into distinct stages: first forming cavities in the semiconductor layer, then forming the gate structure, and finally forming recesses in the gate layer. This segmentation of the complex etching process into manageable stages makes the manufacturing more controllable and easier to implement, reducing the overall manufacturing complexity while achieving parasitic capacitance reduction.
3Object-generated harmful factors
If gate layer is etched to form recess, then parasitic capacitance is reduced, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by first forming the cavities in the semiconductor layer before forming the gate structure, and then forming recesses in the gate layer after the gate is formed. This sequential preliminary preparation of structural features simplifies the overall device complexity by establishing a clear fabrication sequence, making each subsequent step more straightforward while achieving parasitic capacitance reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces parasitic capacitance and enhances the performance of semiconductor devices by creating an isolation sidewall that improves electrical characteristics.
Implementation Method 1
removing a part of the semiconductor layer through etching a sidewall of the semiconductor layer to form a cavity
Implementation Method 2
growing the first sub-channel layer at the first cavity, a proximal sidewall of the first electrode layer, and a proximal sidewall of the second electrode layer through epitaxy
Data Source
AI summary
A semiconductor device and a method for manufacturing the same. A first electrode layer, a semiconductor layer, and a second electrode layer are formed on a substrate. The semiconductor layer is etched form a sidewall to form a cavity. A channel layer is formed at the cavity and sidewalls of the first electrode layer and the second electrode layer. The channel layer includes a first channel part located in the cavity and a second channel part located outside the cavity. The first channel part is filled with a dummy gate layer. The dummy gate layer is etched from a sidewall. The second channel part and the first channel part, which is in contact with upper and lower surfaces of the dummy gate layer are removed to form a recess. The recess is filled with a dielectric material to form an isolation sidewall.