Vertical Semiconductor Structure for Low On-Resistance Switching
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Solution Overview
Problem
Current semiconductor devices face challenges in improving characteristics such as on-resistance, switching speed, and density, particularly in achieving low on-resistance and fast switching while handling large currents.
Innovation Solution
The semiconductor device incorporates a specific configuration with conductive members, semiconductor members, and wiring arrangements, including Schottky contacts and insulating members, to control current flow and reduce on-resistance, featuring a drain-down or source-down configuration with conductive portions and partial regions optimized for reduced resistance and increased channel area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor device structures are used, then manufacturing is simpler, but on-resistance is higher and switching speed is slower
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional vertical channel structures. The channel extends in the vertical direction with height H, creating a vertical transistor architecture where the channel region is defined between source and drain regions in the vertical dimension. This dimensional change increases the effective channel area without increasing the device footprint, thereby reducing on-resistance while maintaining a compact structure suitable for integration.
Solution Approach 2:
The device is segmented into distinct functional regions including source region, channel region, and drain region, with the channel region further divided into multiple sub-regions (first channel region, second channel region, third channel region) with different doping concentrations. This segmentation allows optimization of electrical characteristics in each region, enabling low on-resistance through carefully engineered doping profiles and geometric configurations.
2Productivity
If device density is increased, then more functions are integrated, but manufacturing precision requirements increase
Solution Approach 1:
By utilizing the vertical dimension for channel extension, the patent achieves high device density without requiring extremely small lateral dimensions. The vertical channel height H and depth D provide additional degrees of freedom for design, allowing multiple devices to be integrated in a compact footprint while maintaining manufacturable feature sizes through standard semiconductor fabrication processes.
Solution Approach 2:
The patent employs parameter changes in doping concentrations across different channel regions (first channel region with lower doping, second channel region with intermediate doping, third channel region with higher doping near drain) to optimize device characteristics. This graded doping approach enables precise control of electrical properties while remaining compatible with existing manufacturing capabilities.
3Speed
If switching speed is increased, then gate driver losses increase, but if switching speed is decreased, then device performance deteriorates
Solution Approach 1:
The patent implements local quality variations through different doping concentrations in different channel regions. The first channel region has lower doping for reduced scattering and higher mobility, the second channel region has intermediate doping for transition, and the third channel region has higher doping near the drain for field effect control. This localized optimization enables fast switching with reduced gate driver losses by improving carrier transport efficiency in each region.
Solution Approach 2:
The device structure enables dynamic control of channel characteristics through the vertical field effect, where the channel conductivity can be rapidly modulated by gate voltage. The vertical channel geometry provides strong field effect control, enabling fast switching transitions with reduced gate charge requirements, thereby decreasing gate driver losses while maintaining high switching speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in improved semiconductor device characteristics, including low on-resistance, high-speed switching, reduced gate driver losses, and increased channel density, enabling efficient handling of large currents.
Implementation Method 1
the fourth conductive portion including a facing conductive portion, the third partial region including a facing face facing the facing conductive portion
Data Source
AI summary
According to one embodiment, a semiconductor device includes a first element. The first element includes a first conductive member, a second conductive member, a first semiconductor member, a third conductive member, and a third conductive member wiring. The first conductive member includes a first conductive portion including a first face and a second conductive portion including a second face. The second conductive member includes a third conductive portion including a third face and a fourth conductive portion including a fourth face. The fourth conductive portion includes a facing conductive portion. The first semiconductor member is of a first conductive type. The first semiconductor member includes a first partial region, a second partial region and a third partial region. The third partial region includes a facing face facing the facing conductive portion. The third conductive member wiring is electrically connected to the third conductive member.