Vertical Semiconductor Device Mold Structure for Layer Integration
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Solution Overview
Problem
The integration of semiconductor devices with a vertical structure faces challenges such as layer lifting off and uniform channel layer formation, particularly as the number of laminated layers increases, leading to defects and reliability issues.
Innovation Solution
A method involving the integration of insulating interlayer and stopping layer patterns on a substrate, forming mold structures, and creating channel layer patterns with a thin layer structure, including a blocking dielectric layer, charge storing layer, and tunnel insulating interlayer, while using etching techniques to form step-like edge portions and gate electrodes, reduces defects and ensures uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of laminated layers is increased to achieve high integration, then the integration density is improved, but layer lifting off defects occur frequently
Solution Approach 1:
The patent introduces a mold structure comprising alternating sacrificing layers and insulating interlayer patterns as an intermediary framework. This mold structure serves as a mediator that maintains the integrity of multiple laminated layers during the manufacturing process, preventing lifting off defects while enabling high integration density through vertical stacking of memory cells
Solution Approach 2:
The patent divides the complex multi-layer structure into repeating units of sacrificing layers and insulating interlayer patterns. Each unit forms a discrete segment of the mold structure that can be independently formed and controlled, reducing the cumulative adhesion problems that arise in continuously laminated structures
2Productivity
If vertical structure is formed to achieve high integration, then the device capacity is improved, but uniform channel layer formation becomes challenging
Solution Approach 1:
The mold structure with alternating sacrificing layers and insulating interlayer patterns acts as a precision template that guides the formation of vertical channels. The insulating interlayer patterns provide lateral confinement while the sacrificing layers define the vertical extent, ensuring uniform channel layer formation throughout the vertical structure
Solution Approach 2:
The patent controls the thickness and material properties of the sacrificing layers and insulating interlayer patterns to precisely control the resulting channel layer dimensions. By adjusting the parameters of the mold structure layers, uniform vertical channels with controlled heights and widths are achieved
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces defects due to layer lifting off, allows for the formation of vertical channels with uniform height, and enhances the reliability of the semiconductor device by maintaining uniform electric characteristics.
Implementation Method 1
A portion of the stopping layer and the insulating interlayer for the peripheral circuit device may be etched to expose the substrate in the cell region
Data Source
AI summary
Methods of manufacturing a semiconductor device include forming a stopping layer pattern in a first region of a substrate. A first mold structure is formed in a second region of the substrate that is adjacent the first region. The first mold structure includes first sacrificial patterns and first interlayer patterns stacked alternately. A second mold structure is formed on the first mold structure and the stopping layer pattern. The second mold structure includes second sacrificial patterns and second interlayer patterns stacked alternately. The second mold structure partially covers the stopping layer pattern. A channel pattern is formed and passes through the first mold structure and the second mold structure.