Vertical Semiconductor Device Mold Structure with Sacrificial Layer Oxidation
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Solution Overview
Problem
The challenge in manufacturing vertical semiconductor devices is the difficulty in forming uniform thin layers in narrow high aspect ratio holes, which affects the reliability and integration density of memory devices with vertically stacked transistors.
Innovation Solution
A method involving the formation of a mold structure with sacrificial layers and insulating interlayers, where blocking layers are oxidized to create a wider opening, allowing for the deposition of charge trapping, tunnel insulation, and polysilicon layers, followed by etching to form patterns and control gate electrodes, thereby enhancing the semiconductor pattern characteristics and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high aspect ratio holes are formed to increase integration density, then vertical stacking of transistors is achieved, but uniform thin layers cannot be easily formed in the narrow holes
Solution Approach 1:
The hole formation process is segmented into two stages: first forming high aspect ratio holes through stacked layers, then selectively removing sacrificial layers to create expanded regions. This segmentation allows the hole to serve dual purposes - providing vertical stacking geometry while also accommodating uniform thin layer deposition in the expanded regions.
Solution Approach 2:
Sacrificial layers are preliminarily deposited within the high aspect ratio holes before forming the thin layers. These sacrificial layers are then selectively removed to create expanded regions, ensuring that the thin layers can be uniformly formed in the resulting wider openings without compromising the vertical stacking structure.
2Productivity
If thin layers are formed in narrow high aspect ratio holes, then vertical transistor stacking is achieved, but the reliability of the device decreases due to non-uniform thin layers
Solution Approach 1:
Sacrificial layers are preliminarily formed within the narrow high aspect ratio holes to define the regions where thin layers will be deposited. After the thin layers are uniformly formed in the expanded regions created by removing sacrificial layers, the sacrificial layers are selectively removed. This preliminary action ensures uniform thin layer formation while maintaining vertical transistor stacking, thereby improving device reliability.
Solution Approach 2:
Sacrificial layers act as intermediary structures that enable the formation of uniform thin layers in regions that will become wider openings. These intermediary layers are temporarily present during the thin layer deposition process, ensuring uniformity, and are subsequently removed to create the final device structure with improved reliability.
3Manufacturing precision
If the hole diameter is enlarged to improve thin layer formation, then uniform thin layers can be formed, but the integration density decreases
Solution Approach 1:
The hole structure is segmented into narrow upper portions and expanded lower portions. The narrow upper portions maintain small diameter to preserve integration density and enable vertical stacking, while the expanded lower portions provide sufficient width for uniform thin layer formation. This segmentation resolves the contradiction by allowing different regions to serve different functions.
Solution Approach 2:
The hole geometry transitions from a uniform cylindrical shape to a multi-dimensional structure with varying cross-sectional areas. By creating expanded regions through selective sacrificial layer removal, the hole acquires additional spatial dimensions that accommodate uniform thin layer deposition without increasing the overall footprint, thus maintaining integration density while improving manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method increases the effective diameter of the hole, improves the semiconductor pattern characteristics, and enhances the integration density of vertical semiconductor devices without the need to enlarge the hole, resulting in improved reliability and performance.
Implementation Method 1
Blocking layers are formed by oxidizing portions of the sacrificial layers exposed by the first opening
Data Source
AI summary
Methods of manufacturing vertical semiconductor devices may include forming a mold structure including sacrificial layers and insulating interlayers with a first opening formed therethrough. The sacrificial layers and the insulating interlayers may be stacked repeatedly and alternately on a substrate. The first opening may expose the substrate. Blocking layers may be formed by oxidizing portions of the sacrificial layers exposed by the first opening. A first semiconductor layer pattern, a charge trapping layer pattern and a tunnel insulation layer pattern, respectively, may be formed on the sidewall of the first opening. A second semiconductor layer may be formed on the first polysilicon layer pattern and the bottom of the first opening. The sacrificial layers and the insulating interlayers may be partially removed to form a second opening. The sacrificial layers may be removed to form grooves between the insulating interlayers. Control gate electrodes may be formed in the grooves.