Vertical Semiconductor Device Fabrication via Phase Change
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Solution Overview
Problem
The integration density of vertical semiconductor devices is limited by the use of polysilicon layers in active regions, which results in reduced on-current and operating speed, and requires a chemical vapor deposition (CVD) process for forming tunnel oxide layers, making it difficult to achieve uniform operating characteristics for stacked cell transistors.
Innovation Solution
A method of fabricating vertical semiconductor devices by forming a stack structure with preliminary semiconductor layers that are phase-changed from solid to liquid and back to single crystalline semiconductor layers using processes like laser-induced epitaxial growth, solid-phase epitaxy, or metal-induced crystallization, allowing for the formation of single crystalline semiconductor layers without voids and improving integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polysilicon layers are used in active regions, then manufacturing process is simpler, but on-current is reduced and operating speed decreases
Solution Approach 1:
The patent changes the crystal structure parameter of the semiconductor material from polysilicon to single crystalline semiconductor. This fundamental parameter change transforms the material properties, enabling higher carrier mobility and on-current while maintaining manufacturability through the phase-change process using laser or thermal treatment.
Solution Approach 2:
The patent utilizes phase transitions of semiconductor materials (amorphous to crystalline) to form single crystalline semiconductor layers. By controlling the phase transition through laser irradiation or thermal treatment, the invention achieves high-quality crystalline structures that improve device performance without requiring complex manufacturing processes.
2Ease of manufacture
If polysilicon layers are used in active regions, then ease of manufacture is improved, but integration density is limited
Solution Approach 1:
The invention changes the material parameter from polysilicon to single crystalline semiconductor, which enables better vertical stacking capability and higher integration density. The improved material quality allows for more compact device structures and higher transistor density on the same chip area.
3Quantity of substance
If cell transistors are stacked in vertical direction, then integration density is improved, but uniform operating characteristics become difficult to achieve
Solution Approach 1:
The patent uses single crystalline semiconductor layers which provide homogeneous material properties throughout the vertical stack. This homogeneity ensures uniform electrical characteristics across all transistors in the vertical stack, solving the uniformity problem that arises with polysilicon-based vertical devices.
Solution Approach 2:
By changing from polysilicon to single crystalline semiconductor, the invention achieves better control over material parameters such as carrier mobility and defect density. This parameter change enables more uniform transistor characteristics in vertical stacks, allowing high integration density without sacrificing performance uniformity.
4Ease of manufacture
If polysilicon layers are used in active regions, then ease of manufacture is improved, but tunnel oxide layer formation requires CVD process
Solution Approach 1:
The patent changes the active region material from polysilicon to single crystalline semiconductor. This parameter change enables the formation of tunnel oxide layers through thermal oxidation processes, which are simpler and more reliable than the CVD processes required for polysilicon-based devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the integration density and operating speed of vertical semiconductor devices by forming single crystalline semiconductor layers without voids, improving the uniformity of transistor characteristics and eliminating the need for the CVD process for tunnel oxide formation.
Implementation Method 1
a first preliminary semiconductor layer is formed in partial regions of the openings of the stack structure. The first preliminary semiconductor layer is primarily phase-changed to form a first single crystalline semiconductor layer
Implementation Method 2
using processes like laser-induced epitaxial growth, solid-phase epitaxy, or metal-induced crystallization
Implementation Method 3
changing the phase can be provided by heating the first or second preliminary semiconductor layer to a melting point of silicon using laser light
Implementation Method 4
changing the phase can be provided by heating the first or second preliminary semiconductor layer in a furnace at a temperature of about 600 to about 700 degrees Centigrade for several hours
Data Source
AI summary
A method of fabricating a vertical NAND semiconductor device can include changing a phase of a first preliminary semiconductor layer in an opening from solid to liquid to form a first single crystalline semiconductor layer in the opening and then forming a second preliminary semiconductor layer on the first single crystalline semiconductor layer. The phase of the second preliminary semiconductor layer is changed from solid to liquid to form a second single crystalline semiconductor layer that combines with the first single crystalline semiconductor layers to form a single crystalline semiconductor layer in the opening.