Vertical Semiconductor Pillars for High-Density Flash Memory
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Solution Overview
Problem
Current flash memory devices face challenges in increasing density without encountering operational issues such as severe short channel effects due to smaller device elements, necessitating innovative three-dimensional memory array designs.
Innovation Solution
The formation of vertically stacked memory arrays with semiconductor pillars and charge storage structures, where each pillar is surrounded by semiconductor and dielectric layers, and control gates are formed to create efficient memory cells with improved density and reduced short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell dimensions are reduced to increase density, then memory density is improved, but severe short channel effects occur causing operational problems
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked along the vertical direction, allowing increased storage density without reducing the horizontal footprint of individual cells. This dimensional change enables higher density while maintaining adequate channel lengths to avoid short channel effects.
Solution Approach 2:
The patent implements a nested structure where multiple memory cell layers are stacked vertically, with each layer containing complete memory cell structures including channels, gates, and insulation layers. The layers are nested one above another, sharing common source and drain regions, which increases density while preserving individual cell integrity and operational reliability.
2Quantity of substance
If memory cell size is reduced to increase density, then memory density is improved, but spacing between cells must be reduced causing manufacturing complexity
Solution Approach 1:
The patent merges multiple memory cell layers vertically, sharing common source and drain regions and insulation structures across layers. This consolidation reduces the total number of discrete components and simplifies manufacturing processes compared to creating entirely separate cells, achieving higher density without proportionally increasing manufacturing complexity.
Solution Approach 2:
By stacking memory cells in the vertical dimension rather than packing them horizontally, the patent achieves higher density while maintaining larger effective spacing between active regions. The vertical stacking approach transforms the packing problem from a two-dimensional constraint to a three-dimensional solution, reducing manufacturing complexity.
3Quantity of substance
If traditional two-dimensional arrays are stacked vertically to increase density, then memory density is improved, but severe short channel effects occur due to smaller device elements
Solution Approach 1:
The patent stacks complete memory cell layers vertically, creating three-dimensional structures where the channel length is maintained in the horizontal plane while the vertical stacking provides the density increase. This approach decouples the density improvement from channel length reduction, preventing short channel effects while achieving higher memory density.
Solution Approach 2:
Multiple memory cell structures are nested vertically with shared source and drain regions. This nesting arrangement allows the channel portions to extend vertically between shared source and drain regions, maintaining adequate channel length for reliable operation while achieving high density through vertical integration.
Data Source
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AI summary
Memory arrays and methods of their formation are disclosed. One such memory array has memory-cell strings are formed adjacent to separated substantially vertical, adjacent semiconductor structures, where the separated semiconductor structures couple the memory cells of the respective strings in series. For some embodiments, two dielectric pillars may be formed from a dielectric formed in a single opening, where each of the dielectric pillars has a pair of memory-cell strings adjacent thereto and where at least one memory cell of one of the strings on one of the pillars and at least one memory cell of one of the strings on the other pillar are commonly coupled to an access line.