Vertical Semiconductor Device Raised Pad Contact
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Solution Overview
Problem
It is challenging to form connection wiring with a contact plug on each of the vertically stacked conductive layer patterns in highly integrated semiconductor devices, making it difficult to independently apply electrical signals to memory cells in vertical semiconductor devices.
Innovation Solution
A vertical semiconductor device design featuring interlayer insulating layer patterns and conductive layer patterns with rounded ends, including a pad region with a raised pad portion that protrudes from the surface, allowing contact plugs to penetrate the upper interlayer insulating layer and connect with the conductive layer patterns, preventing short circuits and facilitating electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertically stacked conductive layer patterns are used to increase integration density, then chip size is reduced, but it becomes difficult to form connection wiring with contact plugs on each conductive layer pattern
Solution Approach 1:
The conductive layer patterns extend from the vertical stacking dimension into a horizontal connection region, creating a three-dimensional structure that allows contact plugs to access each layer independently. This dimensional transition enables connection wiring formation on vertically stacked layers without increasing chip footprint.
Solution Approach 2:
The device is divided into a cell block region with vertically stacked memory cells and a connection region where conductive layer patterns extend to receive contact plugs. This segmentation allows independent electrical signal application to each memory cell while maintaining high integration density.
2Reliability
If contact plugs are formed on each vertically stacked conductive layer pattern to enable independent electrical signal application, then memory cell independence is achieved, but manufacturing complexity increases
Solution Approach 1:
The conductive layer patterns serve dual functions: as word lines within the memory cell region and as connection structures extending into the connection region. This multi-functionality reduces the need for separate connection structures, simplifying manufacturing while maintaining electrical signal independence.
Solution Approach 2:
The word lines of vertically stacked memory cells are merged into a common connection region where they can be independently accessed by contact plugs. This merging allows shared infrastructure for signal application while maintaining individual cell control.
Data Source
AI summary
A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns and each having a rounded end, wherein at least one of the conductive layer patterns is configured to extend from one side wall of each of the interlayer insulating layer patterns and include a pad region, and the pad region includes a raised pad portion configured to protrude from a surface of the at least one conductive layer pattern; an upper interlayer insulating layer to cover the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the at least one conductive layer pattern.