Vertical Semiconductor Device Single Crystal Channel Epitaxial Growth
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Solution Overview
Problem
Vertical semiconductor devices face challenges in reducing channel resistance and controlling gate length due to the use of polycrystalline materials, making it difficult to scale down the device area and reduce manufacturing costs.
Innovation Solution
A vertical semiconductor device with a single crystal structure, including a substrate, metallic layers, and a gate stack formed around the channel layer, where the channel layer is grown epitaxially to control gate length and reduce source/drain resistance through the use of conductive layers with high carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If single crystal material is used for the channel, then channel resistance is reduced and integration density is improved, but gate length control becomes difficult
Solution Approach 1:
The patent transitions from planar gate length control to vertical thickness control of the channel layer. By growing the channel layer vertically through epitaxial growth and controlling its thickness, the gate length is precisely determined in the vertical dimension rather than through lateral patterning, resolving the contradiction between using single crystal material and achieving gate length control.
Solution Approach 2:
The patent replaces mechanical/lithographic patterning methods with epitaxial growth control for determining gate length. The thickness of the channel layer, controlled during epitaxial growth, directly determines the gate length, substituting traditional mechanical patterning limitations with precise chemical vapor deposition control.
2Productivity
If single crystal material is used for the channel, then integration density is improved, but source/drain resistance becomes difficult to reduce
Solution Approach 1:
The patent employs a composite structure where a single crystal channel layer is combined with separately optimized source/drain regions. The source/drain regions can be formed with different materials or doping levels than the channel, allowing independent optimization of each region's properties while maintaining the benefits of single crystal channel for high integration density.
Solution Approach 2:
The patent applies different material properties or doping concentrations to different regions of the device. The channel layer maintains single crystal structure for low resistance and high mobility, while source/drain regions are independently optimized with appropriate doping levels to achieve low contact resistance, allowing each region to have the quality needed for its specific function.
3Ease of manufacture
If planar device arrangement is used, then manufacturing is simpler, but device area cannot be scaled down
Solution Approach 1:
The patent transitions from a planar (2D) device layout to a vertical (3D) architecture. The channel layer is grown vertically on the substrate, and the gate stack wraps around the channel in three dimensions. This vertical arrangement allows multiple devices to be stacked in the vertical direction, dramatically reducing the footprint area while maintaining manufacturing feasibility through sequential layer formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves low resistance in the source/drain regions and well-controlled gate length, enabling higher integration density and reduced manufacturing costs by using single crystal materials and epitaxial growth techniques.
Implementation Method 1
The channel layer may be formed by e.g. epitaxial growth, so that the thickness of the channel layer may be well controlled.
Data Source
AI summary
Disclosed are a vertical semiconductor device having a conductive layer, a method of manufacturing the vertical semiconductor device, and an electronic device including the vertical semiconductor device. According to an embodiment, the semiconductor device may include: a substrate; a first metallic layer, a channel layer and a second metallic layer which are sequentially disposed on the substrate; and a gate stack formed around at least a part of a periphery of the channel layer, wherein each of the first metallic layer, the second metallic layer, and the channel layer is of single crystal structure.