Vertical Semiconductor Devices Single-Crystal Channel Integration
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Solution Overview
Problem
Current methods for manufacturing vertical-type semiconductor devices face challenges in achieving high performance and integration due to non-uniform operating characteristics of cell transistors stacked in a vertical direction, particularly with polysilicon channel regions, which result in reduced cell current and durability issues with tunnel oxide layers, limiting the reliability and integration density of NAND flash memory devices.
Innovation Solution
The solution involves forming single-crystalline semiconductor patterns on a substrate with a pillar shape, where transistors are stacked vertically, including a tunnel oxide layer, charge-trapping layer, blocking dielectric layer, and control gate patterns, with metal silicide on the control gate, and using insulation interlayer patterns to insulate and align these components, allowing for precise control and high integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If cell transistors are stacked vertically in a NAND flash memory device, then the degree of integration is improved, but the uniformity of operating characteristics between vertically positioned transistors and substrate transistors deteriorates
Solution Approach 1:
The patent transitions from planar (2D) transistor arrangement to vertical (3D) stacking, enabling higher integration density. Multiple cell transistors are positioned along the vertical dimension rather than spreading them horizontally, thereby increasing the quantity of transistors per unit area while maintaining functional performance through careful design of the vertical structure.
2Ease of manufacture
If a channel region of the cell transistor is formed using polysilicon, then the manufacturing process is simplified, but the operating speed decreases due to reduced cell current
Solution Approach 1:
The patent modifies the material parameter of the channel region from polysilicon to single-crystalline silicon. This material substitution fundamentally changes the electrical properties, providing higher carrier mobility and current drive capability while maintaining compatibility with existing manufacturing processes through selective epitaxial growth or other single-crystal formation techniques.
3Ease of manufacture
If a channel region of the cell transistor is formed using polysilicon, then the manufacturing process is simplified, but the durability of the tunnel oxide layer is lowered
Solution Approach 1:
The patent changes the material parameter of the channel region from polysilicon to single-crystalline silicon, which fundamentally improves the interface quality with the tunnel oxide layer. The single-crystal structure provides a more stable and durable interface, enhancing the longevity and reliability of the tunnel oxide layer while maintaining manufacturing feasibility through established single-crystal growth methods.
4Shape
If an opening is formed with a sidewall inclination angle to create a pillar-shaped channel pattern, then the transistor structure is achieved, but the width of the upper portion must be increased
Solution Approach 1:
The patent employs curved or tapered sidewall profiles instead of straight vertical walls in the opening formation. By introducing curvature or gradual tapering, the structure naturally transitions from a wider upper opening to a narrower lower section, achieving the pillar shape while minimizing the upper width requirement and enabling better scaling to critical dimensions.
5Quantity of substance
If the width of the opening is reduced to a critical dimension level for high integration, then the integration density is improved, but it becomes difficult to achieve with inclined sidewalls
Solution Approach 1:
The patent utilizes curved or tapered sidewall geometries in the opening formation process, which naturally reduce the upper width requirement compared to straight-sided openings. This curved profile approach enables the opening to be scaled down to critical dimension levels while maintaining structural integrity and manufacturability, thereby achieving high integration density without compromising ease of manufacture.
Data Source
AI summary
In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.