Vertical Semiconductor Device Stacked Channel Layers
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Solution Overview
Problem
Horizontal semiconductor devices face challenges in reducing area occupation, leading to increased power consumption and resistance, whereas vertical devices offer potential for area reduction but require innovative manufacturing methods to optimize performance.
Innovation Solution
A vertical semiconductor device is designed with stacked layers, including source/drain and channel layers, where sidewalls of the channel layers extend along different crystal planes to adjust carrier mobility, and a gate stack is formed around the channel layer to control gate length and reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If horizontal device arrangement is used, then device structure is simple, but area occupation increases and device performance deteriorates
Solution Approach 1:
The patent transitions from horizontal device arrangement to vertical device arrangement, changing the spatial dimension of device layout. Multiple devices are stacked vertically along the thickness direction of the substrate, transforming the two-dimensional planar arrangement into a three-dimensional vertical structure. This dimensionality change enables significant area reduction while maintaining device functionality and performance.
2Area of stationary object
If area occupation is reduced, then space is saved, but power consumption and resistance increase
Solution Approach 1:
By stacking devices vertically in the thickness direction rather than arranging them horizontally, the patent reduces area occupation while maintaining electrical performance. The vertical arrangement preserves adequate source-drain-gate dimensional relationships, ensuring proper carrier transport paths and electrical characteristics, thus avoiding increased power consumption and resistance that would result from excessive area reduction.
Solution Approach 2:
The patent optimizes the local structural characteristics of each device layer, ensuring that source, drain, and gate regions maintain appropriate dimensions and spatial relationships within the vertical stack. This local quality optimization ensures that each device maintains proper electrical characteristics and carrier mobility, preventing degradation of power consumption and resistance even as overall area is reduced.
3Area of stationary object
If vertical device arrangement is used, then area occupation is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the device structure into distinct stacked layers including source/drain layers, channel layers, and gate stacks arranged vertically. Each layer is formed through separate manufacturing steps with defined interfaces, allowing precise control of individual layer thicknesses and positions. This segmentation approach enables accurate positioning and dimensional control of each component, meeting the heightened manufacturing precision requirements of vertical devices.
Solution Approach 2:
The patent employs precise control of critical parameters including layer thicknesses, doping concentrations, and material compositions to achieve the required manufacturing precision. By optimizing parameters such as channel layer thickness, source/drain layer dimensions, and gate stack geometry, the patent ensures accurate device characteristics and performance while maintaining the vertical arrangement that reduces area occupation.
4Manufacturing precision
If gate length is controlled through channel layer thickness, then gate length precision improves, but device complexity increases
Solution Approach 1:
The patent utilizes the channel layer thickness itself as the determining factor for gate length, allowing the structure to self-define the critical dimension. The gate stack is positioned such that its length is naturally constrained by the channel layer thickness, eliminating the need for separate gate length definition steps. This self-service approach achieves precise gate length control while avoiding additional manufacturing complexity.
Data Source
AI summary
The present disclosure provides a semiconductor device, a manufacturing method thereof, and an electronic device including the semiconductor device. According to an embodiment of the present disclosure, the semiconductor device may comprise: a substrate; a first device and a second device that are sequentially stacked on the substrate. Each of the first device and the second device comprises: a first source/drain layer, a channel layer, and a second source layer that are sequentially stacked from bottom to top, and a gate stack around at least a part of an outer periphery of the channel layer, wherein sidewalls of the respective channel layers of the first device and the second device extend at least partially along different crystal planes or crystal plane families.