Vertical Semiconductor Device Stacked Word Lines
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Solution Overview
Problem
The integration of memory semiconductor devices is limited by the high cost of equipment required for fine pattern formation, leading to a decrease in memory cell current and restricted degrees of integration in two-dimensional devices.
Innovation Solution
A vertical type semiconductor device with a multi-layer structure, featuring vertically stacked word lines and shared common source or bit lines, which minimizes the decrease in memory cell current by optimizing the use of semiconductor substrate area and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional planar memory semiconductor devices are used to increase integration density, then the area occupied by unit memory cells must be reduced through fine pattern formation, but very high-cost equipment is necessary which limits the degree of integration
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertical memory structures. Word lines, bit lines, and source lines are stacked vertically to form multiple layers, allowing integration density to increase without requiring finer lateral patterning. This vertical stacking enables higher capacity while using existing fabrication capabilities.
Solution Approach 2:
The patent implements a nested structure where multiple word lines, bit lines, and source lines are stacked vertically within a single memory cell column. Each layer contains complete sets of memory cell components, creating a tower-like structure that maximizes space utilization and integration density without proportionally increasing manufacturing complexity.
2Manufacturing precision
If fine pattern formation technology is advanced to reduce unit memory cell area, then integration density may increase, but very high-cost equipment is necessary
Solution Approach 1:
Instead of improving lateral patterning precision, the patent achieves higher integration by stacking structures in the vertical dimension. This approach uses standard patterning processes to create multiple layers, avoiding the need for expensive advanced lithography equipment while still achieving high density through vertical stacking of word lines, bit lines, and source lines.
Data Source
AI summary
A vertical type semiconductor device including a first vertical semiconductor device on a semiconductor substrate, a second vertical semiconductor device on the first vertical semiconductor device, and an interconnection between the first and second vertical semiconductor devices.