Vertical Semiconductor Device Superjunction Gate Pad Pitch Optimization
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Solution Overview
Problem
Vertical semiconductor devices with superjunction structures face challenges in achieving high avalanche withstand, turn-off withstand, and reverse recovery withstand due to dynamic avalanche and false firing issues, particularly under high current density conditions.
Innovation Solution
The design incorporates a guard ring structure, RESURF structure, and field plate structure within the voltage withstanding structure region, along with a specific arrangement of parallel pn layers and a n-type isolation region, which reduces electrical field concentration and enhances charge balance, thereby improving breakdown voltage and reducing on-state resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the n-type drift layer is thickened to increase breakdown voltage, then the current capacity decreases due to increased on-state resistance
Solution Approach 1:
The n-type drift layer is segmented into multiple n-type drift regions separated by p-type partition regions, forming a superjunction structure. This segmentation allows each n-type drift region to be thinner (reducing on-state resistance) while the combined structure provides the necessary breakdown voltage through the alternating pn layers that extend depletion regions across the entire structure during reverse bias.
Solution Approach 2:
Different regions of the drift layer have different impurity concentrations optimized for their specific functions. The n-type drift regions have higher impurity concentrations to reduce on-state resistance, while the p-type partition regions have lower concentrations to enable proper depletion extension. This local optimization allows simultaneous achievement of low conduction loss and high breakdown voltage.
2Reliability
If high current density is applied to reduce on-state resistance, then dynamic avalanche and false firing occur under the gate pad electrode
Solution Approach 1:
The superjunction structure implements local quality variations with different repetition pitches in different regions. Under the gate pad electrode, the repetition pitch is specifically optimized to prevent electric field concentration that would cause dynamic avalanche and false firing, while still maintaining low on-state resistance through appropriate carrier density control in the n-type drift regions.
Solution Approach 2:
The p-type partition regions, which initially might seem to increase complexity, actually serve to redistribute the electric field uniformly across the device. By converting the potential harm of electric field concentration into a beneficial uniform field distribution, the structure prevents dynamic avalanche while maintaining the low resistance path needed for high current density operation.
3Ease of manufacture
If the parallel pn layers are configured with uniform width throughout the device, then manufacturing is simplified but avalanche withstand and turn-off withstand are reduced
Solution Approach 1:
The patent implements non-uniform repetition pitches of the parallel pn layers in different device regions. Under the gate pad electrode, a specific repetition pitch is used to optimize avalanche withstand and turn-off withstand by controlling the electric field distribution during transient conditions, while other regions may use different pitches optimized for their specific functions. This local differentiation maintains manufacturing feasibility while significantly improving reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves high avalanche withstand, turn-off withstand, and reverse recovery withstand by minimizing dynamic avalanche and false firing, while maintaining stable switching characteristics and on-state resistance.
Implementation Method 1
the direction in which a depletion layer caused by reverse bias voltage extends when in an off-state
Implementation Method 2
Achieving charge balance means determining each impurity concentration so that the width of the depletion layer spreading inside the n-type drift region and the width of the depletion layer spreading inside the p-type partition region are the same
Implementation Method 3
a channel inversion layer is formed in a p-type well region
Data Source
Figure 1
Figure 2A~2B
Figure 3~4
AI summary
Provided is a vertical semiconductor device 100, and a method of manufacturing the vertical semiconductor device 100, such that it is possible to obtain low on-state resistance, high avalanche withstand, high turn-off withstand, and high reverse recovery withstand. A vertical semiconductor device 100 including an element active portion 3 and a voltage withstanding structure portion 2 has a first main electrode and a gate pad electrode 7 on a first main surface of the element active portion 3, includes first parallel pn layers 10 in a drift layer 16 below the first main electrode, and includes second parallel pn layers 13 below the gate pad electrode 7. The vertical semiconductor device 100 includes a first conductivity type isolation region 20 between the second parallel pn layers 13 below the gate pad electrode 7 and a p-type well region 5 disposed in a surface layer of the drift layer 16, and by the repetition pitch T2 of the second parallel pn layers 13 being shorter than the repetition pitch T1 of the first parallel pn layers 10, it is possible to obtain low on-state resistance, high avalanche withstand, high turn-off withstand, and high reverse recovery withstand.