Vertical Semiconductor Device With Tapered Gate Stack
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Solution Overview
Problem
Horizontal semiconductor devices face challenges in reducing occupied area while maintaining or improving performance due to their parallel electrode arrangement, limiting their ability to optimize device characteristics such as electrostatic characteristics and power consumption.
Innovation Solution
A vertical semiconductor device is developed with a self-aligned gate stack, where the gate stack is formed around the channel layer with a tapered shape to minimize overlap with source/drain regions, reducing parasitic capacitance and allowing for precise control of the gate length through selective epitaxial growth and replacement processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a horizontal device arrangement is used, then the device structure is simple, but it is not easy to reduce the occupied area while maintaining or improving device performance
Solution Approach 1:
The patent transitions from a horizontal device arrangement to a vertical device arrangement, utilizing the height direction as an additional dimension for electrode optimization. This dimensional change allows the source, gate, and drain electrodes to be stacked vertically rather than arranged horizontally, thereby reducing the occupied area on the substrate while providing more degrees of freedom for performance optimization.
2Ease of manufacture
If the gate stack overlaps with source/drain regions, then manufacturing is easier, but parasitic capacitance increases
Solution Approach 1:
The gate stack is designed with an asymmetric shape that gradually tapers as it approaches the channel layer, creating a non-uniform width profile. This asymmetric geometry allows the gate stack to be positioned closer to the channel layer without excessive overlap with source/drain regions, thereby reducing parasitic capacitance while maintaining manufacturing feasibility through selective epitaxial growth.
Solution Approach 2:
The patent employs selective epitaxial growth to precisely control the dimensions and shape of the gate stack, particularly its width and height parameters. By adjusting growth conditions and duration, the gate stack can be formed with a tapered profile that minimizes overlap with source/drain regions, thereby reducing parasitic capacitance while maintaining ease of manufacture through a well-established semiconductor fabrication process.
3Manufacturing precision
If the gate length is not precisely controlled, then manufacturing is simpler, but device performance optimization is limited
Solution Approach 1:
The patent utilizes selective epitaxial growth, a self-aligned process where the gate stack forms automatically in the desired position and shape based on the underlying channel layer structure. This self-service mechanism inherently provides precise gate length control without requiring additional alignment steps or complex manufacturing processes, as the epitaxial growth naturally conforms to the channel layer dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The vertical device design enhances device performance by reducing area occupancy, improving electrostatic characteristics, and lowering power consumption through effective control of the gate stack and source/drain layers, while maintaining or improving device performance.
Implementation Method 1
forming a sacrificial gate by selective epitaxial growth on the outer peripheral sidewall of the channel layer
Data Source
AI summary
Disclosed are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic apparatus including the semiconductor device. The semiconductor device may include: a substrate; an active region extending vertically on the substrate, wherein the active region includes a first source/drain layer, a channel layer and a second source/drain layer that are sequentially stacked; a gate stack formed around at least part of an outer peripheral sidewall of the channel layer. A sidewall of the gate stack close to the channel layer is aligned with the outer peripheral sidewall of the channel layer, so as to occupy substantially a same range in a vertical direction, and a part of the gate stack close to the channel layer has a shape that gradually tapers as getting close to the channel layer.