Vertical Semiconductor Element With Tapered P-Column
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing vertical semiconductor elements with super junction structures face a trade-off between on-state resistance and withstand voltage due to processing variations, which affect the balance of electrical charge between n-type and p-type columns, leading to reduced withstand voltage yield.
Innovation Solution
The semiconductor device is configured such that the surplus concentration gradient di/dz satisfies the expression O > ∂i/∂z > -(7.97×10^11*Vmax)^2*10^000, ensuring the desired withstand voltage is achieved without reducing the margin for processing variations by controlling the angle of the p-type column's side surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the concentration of n-columns is increased to reduce on-state resistance, then on-state resistance decreases, but the difference of electrical charge between n-columns and p-columns increases due to processing variation, causing withstand voltage yield to decrease
Solution Approach 1:
The patent applies asymmetry by forming the p-column with a tapered side surface instead of a symmetric cylindrical shape. The side surface of the p-column is inclined relative to the depth direction, creating a tapered structure that compensates for processing variations. This asymmetric geometry allows the depletion layer to expand more effectively and maintains charge balance between n-columns and p-columns even when processing variations occur, thereby improving withstand voltage yield while allowing higher n-column concentration for reduced on-state resistance
2Reliability
If the tapered angle of the p-column side surface is increased to improve margin for processing variation, then withstand voltage becomes more stable, but the central withstand voltage reduces
Solution Approach 1:
The patent applies parameter changes by optimizing the tapered angle of the p-column side surface within a specific range. The tapered angle is controlled to be between 5 degrees and 30 degrees relative to the depth direction. This parameter optimization achieves the right balance: the taper is sufficient to provide margin for processing variation and maintain charge balance, but not so excessive that it reduces the central withstand voltage. This controlled parameter change resolves the contradiction between stability and strength
Data Source
AI summary
A semiconductor device includes a vertical semiconductor element having a super junction structure constructed of a first conductivity-type drift layer disposed on a surface of a semiconductor substrate and second conductivity-type regions having a stripe shape defining a longitudinal direction in one direction and being arranged at a predetermined column pitch in the drift layer. When a surplus concentration obtained by dividing a difference between an electrical charge of the second conductivity-type region and an electrical charge of a first conductivity-type region by the column pitch is i, a depth of the super junction structure is z, a surplus concentration gradient as a change of the surplus concentration i per unit depth dz is di/dz, and a central withstand voltage in which a margin is added to a desired withstand voltage is Vmax, the super junction structure is configured such that the surplus concentration gradient di/dz satisfies a relation of0>ⅆiⅆz>-(7.97×1011Vmax)2·110000.